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28aaa58fa6
DELAY takes microseconds not milliseconds, so 100 was too low. Moreover,
when enabling hw.pci.clear_pcib, PCI emeration would still stop at one
of the first bridges, but by asserting PERST for the rest of the reset
sequence that appears to be reliably addressed.
Fixes:
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.. | ||
fe310_aon.c | ||
files.sifive | ||
fu740_pci_dw.c | ||
sifive_gpio.c | ||
sifive_prci.c | ||
sifive_spi.c | ||
sifive_uart.c |