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4b7975ecdc
This doesn't represent the mac_type but if the DMA engine support extended descriptors. Read the HW_FEATURE register to learn if the DMA engine supports it. No functional changes intended.
129 lines
3.8 KiB
C
129 lines
3.8 KiB
C
/*-
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* Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Ethernet media access controller (EMAC)
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* Chapter 17, Altera Cyclone V Device Handbook (CV-5V2 2014.07.22)
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*
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* EMAC is an instance of the Synopsys DesignWare 3504-0
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* Universal 10/100/1000 Ethernet MAC (DWC_gmac).
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*/
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#ifndef __IF_DWCVAR_H__
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#define __IF_DWCVAR_H__
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/*
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* Driver data and defines.
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*/
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#define RX_DESC_COUNT 1024
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#define RX_DESC_SIZE (sizeof(struct dwc_hwdesc) * RX_DESC_COUNT)
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#define TX_DESC_COUNT 1024
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#define TX_MAP_COUNT TX_DESC_COUNT
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#define TX_DESC_SIZE (sizeof(struct dwc_hwdesc) * TX_DESC_COUNT)
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#define TX_MAP_MAX_SEGS 32
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#define DMA_DEFAULT_PBL 8
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struct dwc_bufmap {
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bus_dmamap_t map;
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struct mbuf *mbuf;
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/* Only used for TX descirptors */
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int last_desc_idx;
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};
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struct dwc_softc {
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struct resource *res[2];
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device_t dev;
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phandle_t node;
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int mii_clk;
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device_t miibus;
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struct mii_data * mii_softc;
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if_t ifp;
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int if_flags;
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struct mtx mtx;
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void * intr_cookie;
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struct callout dwc_callout;
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bool link_is_up;
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bool is_attached;
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bool is_detaching;
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int tx_watchdog_count;
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int stats_harvest_count;
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int phy_mode;
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/* clocks and reset */
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clk_t clk_stmmaceth;
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clk_t clk_pclk;
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hwreset_t rst_stmmaceth;
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hwreset_t rst_ahb;
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/* DMA config */
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uint32_t txpbl; /* TX Burst lenght */
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uint32_t rxpbl; /* RX Burst lenght */
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bool nopblx8;
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bool fixed_burst;
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bool mixed_burst;
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bool aal;
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bool dma_ext_desc;
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/* RX */
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bus_dma_tag_t rxdesc_tag;
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bus_dmamap_t rxdesc_map;
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struct dwc_hwdesc *rxdesc_ring;
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bus_addr_t rxdesc_ring_paddr;
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bus_dma_tag_t rxbuf_tag;
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struct dwc_bufmap rxbuf_map[RX_DESC_COUNT];
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uint32_t rx_idx;
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/* TX */
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bus_dma_tag_t txdesc_tag;
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bus_dmamap_t txdesc_map;
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struct dwc_hwdesc *txdesc_ring;
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bus_addr_t txdesc_ring_paddr;
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bus_dma_tag_t txbuf_tag;
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struct dwc_bufmap txbuf_map[TX_DESC_COUNT];
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uint32_t tx_desc_head;
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uint32_t tx_desc_tail;
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uint32_t tx_map_head;
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uint32_t tx_map_tail;
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int tx_desccount;
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int tx_mapcount;
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};
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#define READ4(_sc, _reg) \
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bus_read_4((_sc)->res[0], _reg)
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#define WRITE4(_sc, _reg, _val) \
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bus_write_4((_sc)->res[0], _reg, _val)
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#define DWC_LOCK(sc) mtx_lock(&(sc)->mtx)
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#define DWC_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
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#define DWC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED)
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#define DWC_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED)
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#endif /* __IF_DWCVAR_H__ */
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