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dwc: Remove if_dwc_mac_type

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This doesn't represent the mac_type but if the DMA engine support
extended descriptors.
Read the HW_FEATURE register to learn if the DMA engine supports it.

No functional changes intended.
This commit is contained in:
Emmanuel Vadot 2023-10-04 21:10:47 +02:00
parent cef444d068
commit 4b7975ecdc
9 changed files with 22 additions and 46 deletions
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14
sys/dev/dwc/dwc1000_core.c
View file

@ -281,7 +281,11 @@ dwc_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
crc = ether_crc32_le(LLADDR(sdl), ETHER_ADDR_LEN);
/* Take lower 8 bits and reverse it */
val = bitreverse(~crc & 0xff);
if (ctx->sc->mactype != DWC_GMAC_EXT_DESC)
/*
* TODO: There is probably a HW_FEATURES bit which isn't
* related to the extended descriptors that describe this
*/
if (!ctx->sc->dma_ext_desc)
val >>= 2; /* Only need lower 6 bits */
hashreg = (val >> 5);
hashbit = (val & 31);
@ -302,7 +306,11 @@ dwc1000_setup_rxfilter(struct dwc_softc *sc)
DWC_ASSERT_LOCKED(sc);
ifp = sc->ifp;
nhash = sc->mactype != DWC_GMAC_EXT_DESC ? 2 : 8;
/*
* TODO: There is probably a HW_FEATURES bit which isn't
* related to the extended descriptors that describe this
*/
nhash = sc->dma_ext_desc == false ? 2 : 8;
/*
* Set the multicast (group) filter hash.
@ -335,7 +343,7 @@ dwc1000_setup_rxfilter(struct dwc_softc *sc)
WRITE4(sc, MAC_ADDRESS_LOW(0), lo);
WRITE4(sc, MAC_ADDRESS_HIGH(0), hi);
WRITE4(sc, MAC_FRAME_FILTER, ffval);
if (sc->mactype != DWC_GMAC_EXT_DESC) {
if (!sc->dma_ext_desc) {
WRITE4(sc, GMAC_MAC_HTLOW, ctx.hash[0]);
WRITE4(sc, GMAC_MAC_HTHIGH, ctx.hash[1]);
} else {

12
sys/dev/dwc/dwc1000_dma.c
View file

@ -201,7 +201,7 @@ dwc_setup_txdesc(struct dwc_softc *sc, int idx, bus_addr_t paddr,
desc1 = 0;
--sc->tx_desccount;
} else {
if (sc->mactype != DWC_GMAC_EXT_DESC) {
if (!sc->dma_ext_desc) {
desc0 = 0;
desc1 = NTDESC1_TCH | len | flags;
if (first)
@ -233,7 +233,7 @@ dwc_setup_rxdesc(struct dwc_softc *sc, int idx, bus_addr_t paddr)
nidx = next_rxidx(sc, idx);
sc->rxdesc_ring[idx].addr2 = sc->rxdesc_ring_paddr +
(nidx * sizeof(struct dwc_hwdesc));
if (sc->mactype != DWC_GMAC_EXT_DESC)
if (!sc->dma_ext_desc)
sc->rxdesc_ring[idx].desc1 = NRDESC1_RCH |
MIN(MCLBYTES, NRDESC1_RBS1_MASK);
else
@ -282,12 +282,12 @@ dma1000_setup_txbuf(struct dwc_softc *sc, int idx, struct mbuf **mp)
if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) {
if ((m->m_pkthdr.csum_flags & (CSUM_TCP|CSUM_UDP)) != 0) {
if (sc->mactype != DWC_GMAC_EXT_DESC)
if (!sc->dma_ext_desc)
flags = NTDESC1_CIC_FULL;
else
flags = ETDESC0_CIC_FULL;
} else {
if (sc->mactype != DWC_GMAC_EXT_DESC)
if (!sc->dma_ext_desc)
flags = NTDESC1_CIC_HDR;
else
flags = ETDESC0_CIC_HDR;
@ -646,6 +646,10 @@ dma1000_init(struct dwc_softc *sc)
WRITE4(sc, BUS_MODE, reg);
reg = READ4(sc, HW_FEATURE);
if (reg & HW_FEATURE_EXT_DESCRIPTOR)
sc->dma_ext_desc = true;
/*
* DMA must be stop while changing descriptor list addresses.
*/

2
sys/dev/dwc/dwc1000_reg.h
View file

@ -275,7 +275,9 @@
#define CURRENT_HOST_RECEIVE_DESCR 0x104C
#define CURRENT_HOST_TRANSMIT_BUF_ADDR 0x1050
#define CURRENT_HOST_RECEIVE_BUF_ADDR 0x1054
#define HW_FEATURE 0x1058
#define HW_FEATURE_EXT_DESCRIPTOR (1 << 24)
#define DWC_GMAC_NORMAL_DESC 0x1
#define DWC_GMAC_EXT_DESC 0x2

1
sys/dev/dwc/if_dwc.c
View file

@ -505,7 +505,6 @@ dwc_attach(device_t dev)
sc->tx_desccount = TX_DESC_COUNT;
sc->tx_mapcount = 0;
sc->mii_clk = IF_DWC_MII_CLK(dev);
sc->mactype = IF_DWC_MAC_TYPE(dev);
sc->node = ofw_bus_get_node(dev);
sc->phy_mode = mii_fdt_get_contype(sc->node);

8
sys/dev/dwc/if_dwc_aw.c
View file

@ -122,13 +122,6 @@ a20_if_dwc_init(device_t dev)
return (0);
}
static int
a20_if_dwc_mac_type(device_t dev)
{
return (DWC_GMAC_NORMAL_DESC);
}
static int
a20_if_dwc_mii_clk(device_t dev)
{
@ -140,7 +133,6 @@ static device_method_t a20_dwc_methods[] = {
DEVMETHOD(device_probe, a20_if_dwc_probe),
DEVMETHOD(if_dwc_init, a20_if_dwc_init),
DEVMETHOD(if_dwc_mac_type, a20_if_dwc_mac_type),
DEVMETHOD(if_dwc_mii_clk, a20_if_dwc_mii_clk),
DEVMETHOD_END

13
sys/dev/dwc/if_dwc_if.m
View file

@ -36,12 +36,6 @@ CODE {
return (0);
}
static int
if_dwc_default_mac_type(device_t dev)
{
return (DWC_GMAC_EXT_DESC);
}
static int
if_dwc_default_mii_clk(device_t dev)
{
@ -65,13 +59,6 @@ METHOD int init {
device_t dev;
} DEFAULT if_dwc_default_init;
#
# Return the DWC MAC type (descriptor type).
#
METHOD int mac_type {
device_t dev;
} DEFAULT if_dwc_default_mac_type;
#
# Return the DWC MII clock for a specific hardware.
#

8
sys/dev/dwc/if_dwc_rk.c
View file

@ -578,13 +578,6 @@ if_dwc_rk_init(device_t dev)
return (0);
}
static int
if_dwc_rk_mac_type(device_t dev)
{
return (DWC_GMAC_NORMAL_DESC);
}
static int
if_dwc_rk_mii_clk(device_t dev)
{
@ -610,7 +603,6 @@ static device_method_t if_dwc_rk_methods[] = {
DEVMETHOD(device_probe, if_dwc_rk_probe),
DEVMETHOD(if_dwc_init, if_dwc_rk_init),
DEVMETHOD(if_dwc_mac_type, if_dwc_rk_mac_type),
DEVMETHOD(if_dwc_mii_clk, if_dwc_rk_mii_clk),
DEVMETHOD(if_dwc_set_speed, if_dwc_rk_set_speed),

8
sys/dev/dwc/if_dwc_socfpga.c
View file

@ -75,13 +75,6 @@ if_dwc_socfpga_init(device_t dev)
return (0);
}
static int
if_dwc_socfpga_mac_type(device_t dev)
{
return (DWC_GMAC_EXT_DESC);
}
static int
if_dwc_socfpga_mii_clk(device_t dev)
{
@ -100,7 +93,6 @@ static device_method_t dwc_socfpga_methods[] = {
DEVMETHOD(device_probe, if_dwc_socfpga_probe),
DEVMETHOD(if_dwc_init, if_dwc_socfpga_init),
DEVMETHOD(if_dwc_mac_type, if_dwc_socfpga_mac_type),
DEVMETHOD(if_dwc_mii_clk, if_dwc_socfpga_mii_clk),
DEVMETHOD_END

2
sys/dev/dwc/if_dwcvar.h
View file

@ -61,7 +61,6 @@ struct dwc_softc {
struct resource *res[2];
device_t dev;
phandle_t node;
int mactype;
int mii_clk;
device_t miibus;
struct mii_data * mii_softc;
@ -90,6 +89,7 @@ struct dwc_softc {
bool fixed_burst;
bool mixed_burst;
bool aal;
bool dma_ext_desc;
/* RX */
bus_dma_tag_t rxdesc_tag;