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https://github.com/dart-lang/sdk
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c05f1f9448
The first invocation of a native functions goes into LinkNativeCall which determines the final entry point and patches the object pool entry. When running precompiled code, this makes deserializing the object pool entries for native functions easy, they all initially point to a single entry (LinkNativeCall). BUG= R=rmacnak@google.com Review URL: https://codereview.chromium.org//1294113004 .
405 lines
14 KiB
C++
405 lines
14 KiB
C++
// Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file
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// for details. All rights reserved. Use of this source code is governed by a
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// BSD-style license that can be found in the LICENSE file.
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#include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM64.
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#if defined(TARGET_ARCH_ARM64)
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#include "vm/assembler.h"
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#include "vm/constants_arm64.h"
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#include "vm/cpu.h"
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#include "vm/instructions.h"
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#include "vm/object.h"
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namespace dart {
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CallPattern::CallPattern(uword pc, const Code& code)
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: object_pool_(ObjectPool::Handle(code.GetObjectPool())),
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end_(pc),
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ic_data_load_end_(0),
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target_address_pool_index_(-1),
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ic_data_(ICData::Handle()) {
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ASSERT(code.ContainsInstructionAt(pc));
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// Last instruction: blr ip0.
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ASSERT(*(reinterpret_cast<uint32_t*>(end_) - 1) == 0xd63f0200);
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Register reg;
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ic_data_load_end_ =
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InstructionPattern::DecodeLoadWordFromPool(end_ - Instr::kInstrSize,
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®,
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&target_address_pool_index_);
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ASSERT(reg == IP0);
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}
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NativeCallPattern::NativeCallPattern(uword pc, const Code& code)
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: object_pool_(ObjectPool::Handle(code.GetObjectPool())),
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end_(pc),
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native_function_pool_index_(-1),
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target_address_pool_index_(-1) {
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ASSERT(code.ContainsInstructionAt(pc));
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// Last instruction: blr ip0.
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ASSERT(*(reinterpret_cast<uint32_t*>(end_) - 1) == 0xd63f0200);
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Register reg;
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uword native_function_load_end =
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InstructionPattern::DecodeLoadWordFromPool(end_ - Instr::kInstrSize,
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®,
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&target_address_pool_index_);
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ASSERT(reg == IP0);
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InstructionPattern::DecodeLoadWordFromPool(native_function_load_end,
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®,
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&native_function_pool_index_);
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ASSERT(reg == R5);
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}
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uword NativeCallPattern::target() const {
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return object_pool_.RawValueAt(target_address_pool_index_);
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}
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void NativeCallPattern::set_target(uword target_address) const {
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object_pool_.SetRawValueAt(target_address_pool_index_, target_address);
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// No need to flush the instruction cache, since the code is not modified.
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}
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NativeFunction NativeCallPattern::native_function() const {
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return reinterpret_cast<NativeFunction>(
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object_pool_.RawValueAt(native_function_pool_index_));
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}
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void NativeCallPattern::set_native_function(NativeFunction func) const {
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object_pool_.SetRawValueAt(native_function_pool_index_,
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reinterpret_cast<uword>(func));
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}
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intptr_t InstructionPattern::OffsetFromPPIndex(intptr_t index) {
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return Array::element_offset(index);
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}
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// Decodes a load sequence ending at 'end' (the last instruction of the load
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// sequence is the instruction before the one at end). Returns a pointer to
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// the first instruction in the sequence. Returns the register being loaded
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// and the loaded object in the output parameters 'reg' and 'obj'
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// respectively.
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uword InstructionPattern::DecodeLoadObject(uword end,
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const ObjectPool& object_pool,
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Register* reg,
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Object* obj) {
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// 1. LoadWordFromPool
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// or
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// 2. LoadDecodableImmediate
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uword start = 0;
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Instr* instr = Instr::At(end - Instr::kInstrSize);
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if (instr->IsLoadStoreRegOp()) {
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// Case 1.
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intptr_t index = 0;
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start = DecodeLoadWordFromPool(end, reg, &index);
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*obj = object_pool.ObjectAt(index);
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} else {
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// Case 2.
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intptr_t value = 0;
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start = DecodeLoadWordImmediate(end, reg, &value);
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*obj = reinterpret_cast<RawObject*>(value);
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}
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return start;
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}
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// Decodes a load sequence ending at 'end' (the last instruction of the load
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// sequence is the instruction before the one at end). Returns a pointer to
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// the first instruction in the sequence. Returns the register being loaded
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// and the loaded immediate value in the output parameters 'reg' and 'value'
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// respectively.
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uword InstructionPattern::DecodeLoadWordImmediate(uword end,
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Register* reg,
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intptr_t* value) {
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// 1. LoadWordFromPool
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// or
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// 2. LoadWordFromPool
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// orri
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// or
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// 3. LoadPatchableImmediate
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uword start = end - Instr::kInstrSize;
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Instr* instr = Instr::At(start);
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bool odd = false;
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// Case 2.
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if (instr->IsLogicalImmOp()) {
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ASSERT(instr->Bit(29) == 1);
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odd = true;
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// end points at orri so that we can pass it to DecodeLoadWordFromPool.
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end = start;
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start -= Instr::kInstrSize;
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instr = Instr::At(start);
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// Case 2 falls through to case 1.
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}
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// Case 1.
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if (instr->IsLoadStoreRegOp()) {
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start = DecodeLoadWordFromPool(end, reg, value);
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if (odd) {
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*value |= 1;
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}
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return start;
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}
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// Case 3.
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// movk dst, imm3, 3; movk dst, imm2, 2; movk dst, imm1, 1; movz dst, imm0, 0
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ASSERT(instr->IsMoveWideOp());
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ASSERT(instr->Bits(29, 2) == 3);
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ASSERT(instr->HWField() == 3); // movk dst, imm3, 3
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*reg = instr->RdField();
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*value = static_cast<int64_t>(instr->Imm16Field()) << 48;
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start -= Instr::kInstrSize;
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instr = Instr::At(start);
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ASSERT(instr->IsMoveWideOp());
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ASSERT(instr->Bits(29, 2) == 3);
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ASSERT(instr->HWField() == 2); // movk dst, imm2, 2
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ASSERT(instr->RdField() == *reg);
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*value |= static_cast<int64_t>(instr->Imm16Field()) << 32;
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start -= Instr::kInstrSize;
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instr = Instr::At(start);
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ASSERT(instr->IsMoveWideOp());
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ASSERT(instr->Bits(29, 2) == 3);
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ASSERT(instr->HWField() == 1); // movk dst, imm1, 1
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ASSERT(instr->RdField() == *reg);
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*value |= static_cast<int64_t>(instr->Imm16Field()) << 16;
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start -= Instr::kInstrSize;
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instr = Instr::At(start);
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ASSERT(instr->IsMoveWideOp());
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ASSERT(instr->Bits(29, 2) == 2);
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ASSERT(instr->HWField() == 0); // movz dst, imm0, 0
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ASSERT(instr->RdField() == *reg);
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*value |= static_cast<int64_t>(instr->Imm16Field());
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return start;
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}
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// Decodes a load sequence ending at 'end' (the last instruction of the load
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// sequence is the instruction before the one at end). Returns a pointer to
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// the first instruction in the sequence. Returns the register being loaded
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// and the index in the pool being read from in the output parameters 'reg'
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// and 'index' respectively.
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uword InstructionPattern::DecodeLoadWordFromPool(uword end,
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Register* reg,
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intptr_t* index) {
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// 1. ldr dst, [pp, offset]
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// or
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// 2. add dst, pp, #offset_hi12
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// ldr dst [dst, #offset_lo12]
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// or
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// 3. movz dst, low_offset, 0
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// movk dst, hi_offset, 1 (optional)
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// ldr dst, [pp, dst]
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uword start = end - Instr::kInstrSize;
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Instr* instr = Instr::At(start);
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intptr_t offset = 0;
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// Last instruction is always an ldr into a 64-bit X register.
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ASSERT(instr->IsLoadStoreRegOp() && (instr->Bit(22) == 1) &&
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(instr->Bits(30, 2) == 3));
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// Grab the destination register from the ldr instruction.
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*reg = instr->RtField();
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if (instr->Bit(24) == 1) {
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// base + scaled unsigned 12-bit immediate offset.
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// Case 1.
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offset |= (instr->Imm12Field() << 3);
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if (instr->RnField() == *reg) {
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start -= Instr::kInstrSize;
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instr = Instr::At(start);
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ASSERT(instr->IsAddSubImmOp());
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ASSERT(instr->RnField() == PP);
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ASSERT(instr->RdField() == *reg);
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offset |= (instr->Imm12Field() << 12);
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}
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} else {
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ASSERT(instr->Bits(10, 2) == 2);
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// We have to look at the preceding one or two instructions to find the
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// offset.
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start -= Instr::kInstrSize;
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instr = Instr::At(start);
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ASSERT(instr->IsMoveWideOp());
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ASSERT(instr->RdField() == *reg);
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if (instr->Bits(29, 2) == 2) { // movz dst, low_offset, 0
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ASSERT(instr->HWField() == 0);
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offset = instr->Imm16Field();
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// no high offset.
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} else {
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ASSERT(instr->Bits(29, 2) == 3); // movk dst, high_offset, 1
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ASSERT(instr->HWField() == 1);
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offset = instr->Imm16Field() << 16;
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start -= Instr::kInstrSize;
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instr = Instr::At(start);
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ASSERT(instr->IsMoveWideOp());
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ASSERT(instr->RdField() == *reg);
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ASSERT(instr->Bits(29, 2) == 2); // movz dst, low_offset, 0
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ASSERT(instr->HWField() == 0);
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offset |= instr->Imm16Field();
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}
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}
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// PP is untagged on ARM64.
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ASSERT(Utils::IsAligned(offset, 8));
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*index = ObjectPool::IndexFromOffset(offset - kHeapObjectTag);
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return start;
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}
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// Encodes a load sequence ending at 'end'. Encodes a fixed length two
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// instruction load from the pool pointer in PP using the destination
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// register reg as a temporary for the base address.
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// Assumes that the location has already been validated for patching.
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void InstructionPattern::EncodeLoadWordFromPoolFixed(uword end,
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int32_t offset) {
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uword start = end - Instr::kInstrSize;
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Instr* instr = Instr::At(start);
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const int32_t upper12 = offset & 0x00fff000;
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const int32_t lower12 = offset & 0x00000fff;
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ASSERT((offset & 0xff000000) == 0); // Can't encode > 24 bits.
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ASSERT(((lower12 >> 3) << 3) == lower12); // 8-byte aligned.
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instr->SetImm12Bits(instr->InstructionBits(), lower12 >> 3);
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start -= Instr::kInstrSize;
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instr = Instr::At(start);
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instr->SetImm12Bits(instr->InstructionBits(), upper12 >> 12);
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instr->SetInstructionBits(instr->InstructionBits() | B22);
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}
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RawICData* CallPattern::IcData() {
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if (ic_data_.IsNull()) {
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Register reg;
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InstructionPattern::DecodeLoadObject(ic_data_load_end_,
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object_pool_,
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®,
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&ic_data_);
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ASSERT(reg == R5);
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}
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return ic_data_.raw();
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}
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uword CallPattern::TargetAddress() const {
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return object_pool_.RawValueAt(target_address_pool_index_);
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}
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void CallPattern::SetTargetAddress(uword target_address) const {
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object_pool_.SetRawValueAt(target_address_pool_index_, target_address);
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// No need to flush the instruction cache, since the code is not modified.
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}
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void CallPattern::InsertAt(uword pc, uword target_address) {
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Instr* movz0 = Instr::At(pc + (0 * Instr::kInstrSize));
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Instr* movk1 = Instr::At(pc + (1 * Instr::kInstrSize));
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Instr* movk2 = Instr::At(pc + (2 * Instr::kInstrSize));
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Instr* movk3 = Instr::At(pc + (3 * Instr::kInstrSize));
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Instr* blr = Instr::At(pc + (4 * Instr::kInstrSize));
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const uint32_t w0 = Utils::Low32Bits(target_address);
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const uint32_t w1 = Utils::High32Bits(target_address);
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const uint16_t h0 = Utils::Low16Bits(w0);
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const uint16_t h1 = Utils::High16Bits(w0);
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const uint16_t h2 = Utils::Low16Bits(w1);
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const uint16_t h3 = Utils::High16Bits(w1);
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movz0->SetMoveWideBits(MOVZ, IP0, h0, 0, kDoubleWord);
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movk1->SetMoveWideBits(MOVK, IP0, h1, 1, kDoubleWord);
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movk2->SetMoveWideBits(MOVK, IP0, h2, 2, kDoubleWord);
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movk3->SetMoveWideBits(MOVK, IP0, h3, 3, kDoubleWord);
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blr->SetUnconditionalBranchRegBits(BLR, IP0);
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ASSERT(kLengthInBytes == 5 * Instr::kInstrSize);
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CPU::FlushICache(pc, kLengthInBytes);
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}
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JumpPattern::JumpPattern(uword pc, const Code& code) : pc_(pc) { }
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bool JumpPattern::IsValid() const {
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Instr* movz0 = Instr::At(pc_ + (0 * Instr::kInstrSize));
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Instr* movk1 = Instr::At(pc_ + (1 * Instr::kInstrSize));
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Instr* movk2 = Instr::At(pc_ + (2 * Instr::kInstrSize));
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Instr* movk3 = Instr::At(pc_ + (3 * Instr::kInstrSize));
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Instr* br = Instr::At(pc_ + (4 * Instr::kInstrSize));
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return (movz0->IsMoveWideOp()) && (movz0->Bits(29, 2) == 2) &&
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(movk1->IsMoveWideOp()) && (movk1->Bits(29, 2) == 3) &&
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(movk2->IsMoveWideOp()) && (movk2->Bits(29, 2) == 3) &&
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(movk3->IsMoveWideOp()) && (movk3->Bits(29, 2) == 3) &&
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(br->IsUnconditionalBranchRegOp()) && (br->Bits(16, 5) == 31);
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}
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uword JumpPattern::TargetAddress() const {
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Instr* movz0 = Instr::At(pc_ + (0 * Instr::kInstrSize));
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Instr* movk1 = Instr::At(pc_ + (1 * Instr::kInstrSize));
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Instr* movk2 = Instr::At(pc_ + (2 * Instr::kInstrSize));
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Instr* movk3 = Instr::At(pc_ + (3 * Instr::kInstrSize));
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const uint16_t imm0 = movz0->Imm16Field();
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const uint16_t imm1 = movk1->Imm16Field();
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const uint16_t imm2 = movk2->Imm16Field();
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const uint16_t imm3 = movk3->Imm16Field();
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const int64_t target =
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(static_cast<int64_t>(imm0)) |
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(static_cast<int64_t>(imm1) << 16) |
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(static_cast<int64_t>(imm2) << 32) |
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(static_cast<int64_t>(imm3) << 48);
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return target;
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}
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void JumpPattern::SetTargetAddress(uword target_address) const {
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Instr* movz0 = Instr::At(pc_ + (0 * Instr::kInstrSize));
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Instr* movk1 = Instr::At(pc_ + (1 * Instr::kInstrSize));
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Instr* movk2 = Instr::At(pc_ + (2 * Instr::kInstrSize));
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Instr* movk3 = Instr::At(pc_ + (3 * Instr::kInstrSize));
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const int32_t movz0_bits = movz0->InstructionBits();
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const int32_t movk1_bits = movk1->InstructionBits();
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const int32_t movk2_bits = movk2->InstructionBits();
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const int32_t movk3_bits = movk3->InstructionBits();
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const uint32_t w0 = Utils::Low32Bits(target_address);
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const uint32_t w1 = Utils::High32Bits(target_address);
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const uint16_t h0 = Utils::Low16Bits(w0);
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const uint16_t h1 = Utils::High16Bits(w0);
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const uint16_t h2 = Utils::Low16Bits(w1);
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const uint16_t h3 = Utils::High16Bits(w1);
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movz0->SetInstructionBits((movz0_bits & ~kImm16Mask) | (h0 << kImm16Shift));
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movk1->SetInstructionBits((movk1_bits & ~kImm16Mask) | (h1 << kImm16Shift));
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movk2->SetInstructionBits((movk2_bits & ~kImm16Mask) | (h2 << kImm16Shift));
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movk3->SetInstructionBits((movk3_bits & ~kImm16Mask) | (h3 << kImm16Shift));
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CPU::FlushICache(pc_, 4 * Instr::kInstrSize);
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}
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ReturnPattern::ReturnPattern(uword pc)
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: pc_(pc) {
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}
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bool ReturnPattern::IsValid() const {
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Instr* bx_lr = Instr::At(pc_);
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const Register crn = ConcreteRegister(LR);
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const int32_t instruction = RET | (static_cast<int32_t>(crn) << kRnShift);
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return bx_lr->InstructionBits() == instruction;
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}
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} // namespace dart
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#endif // defined TARGET_ARCH_ARM64
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