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server: Add ARM support.
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ed59c54dc7
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@ -129,7 +129,7 @@ typedef union
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enum cpu_type
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enum cpu_type
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{
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{
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CPU_x86, CPU_x86_64, CPU_ALPHA, CPU_POWERPC, CPU_SPARC
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CPU_x86, CPU_x86_64, CPU_ALPHA, CPU_POWERPC, CPU_ARM, CPU_SPARC
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};
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};
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typedef int cpu_type_t;
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typedef int cpu_type_t;
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@ -146,6 +146,7 @@ typedef struct
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struct { unsigned __int64 fir;
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struct { unsigned __int64 fir;
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unsigned int psr, __pad; } alpha_regs;
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unsigned int psr, __pad; } alpha_regs;
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struct { unsigned int iar, msr, ctr, lr, dar, dsisr, trap, __pad; } powerpc_regs;
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struct { unsigned int iar, msr, ctr, lr, dar, dsisr, trap, __pad; } powerpc_regs;
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struct { unsigned int sp, lr, pc, cpsr; } arm_regs;
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struct { unsigned int psr, pc, npc, y, wim, tbr; } sparc_regs;
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struct { unsigned int psr, pc, npc, y, wim, tbr; } sparc_regs;
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} ctl;
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} ctl;
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union
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union
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@ -156,6 +157,7 @@ typedef struct
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struct { unsigned __int64 v0, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, t10, t11, t12,
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struct { unsigned __int64 v0, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, t10, t11, t12,
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s0, s1, s2, s3, s4, s5, s6, a0, a1, a2, a3, a4, a5, at; } alpha_regs;
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s0, s1, s2, s3, s4, s5, s6, a0, a1, a2, a3, a4, a5, at; } alpha_regs;
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struct { unsigned int gpr[32], cr, xer; } powerpc_regs;
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struct { unsigned int gpr[32], cr, xer; } powerpc_regs;
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struct { unsigned int r[13]; } arm_regs;
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struct { unsigned int g[8], o[8], l[8], i[8]; } sparc_regs;
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struct { unsigned int g[8], o[8], l[8], i[8]; } sparc_regs;
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} integer;
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} integer;
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union
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union
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@ -5515,6 +5517,6 @@ union generic_reply
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struct set_cursor_reply set_cursor_reply;
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struct set_cursor_reply set_cursor_reply;
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};
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};
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#define SERVER_PROTOCOL_VERSION 408
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#define SERVER_PROTOCOL_VERSION 409
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#endif /* __WINE_WINE_SERVER_PROTOCOL_H */
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#endif /* __WINE_WINE_SERVER_PROTOCOL_H */
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@ -145,7 +145,7 @@ typedef union
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/* supported CPU types */
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/* supported CPU types */
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enum cpu_type
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enum cpu_type
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{
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{
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CPU_x86, CPU_x86_64, CPU_ALPHA, CPU_POWERPC, CPU_SPARC
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CPU_x86, CPU_x86_64, CPU_ALPHA, CPU_POWERPC, CPU_ARM, CPU_SPARC
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};
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};
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typedef int cpu_type_t;
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typedef int cpu_type_t;
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@ -162,6 +162,7 @@ typedef struct
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struct { unsigned __int64 fir;
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struct { unsigned __int64 fir;
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unsigned int psr, __pad; } alpha_regs;
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unsigned int psr, __pad; } alpha_regs;
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struct { unsigned int iar, msr, ctr, lr, dar, dsisr, trap, __pad; } powerpc_regs;
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struct { unsigned int iar, msr, ctr, lr, dar, dsisr, trap, __pad; } powerpc_regs;
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struct { unsigned int sp, lr, pc, cpsr; } arm_regs;
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struct { unsigned int psr, pc, npc, y, wim, tbr; } sparc_regs;
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struct { unsigned int psr, pc, npc, y, wim, tbr; } sparc_regs;
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} ctl; /* selected by SERVER_CTX_CONTROL */
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} ctl; /* selected by SERVER_CTX_CONTROL */
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union
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union
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@ -172,6 +173,7 @@ typedef struct
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struct { unsigned __int64 v0, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, t10, t11, t12,
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struct { unsigned __int64 v0, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, t10, t11, t12,
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s0, s1, s2, s3, s4, s5, s6, a0, a1, a2, a3, a4, a5, at; } alpha_regs;
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s0, s1, s2, s3, s4, s5, s6, a0, a1, a2, a3, a4, a5, at; } alpha_regs;
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struct { unsigned int gpr[32], cr, xer; } powerpc_regs;
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struct { unsigned int gpr[32], cr, xer; } powerpc_regs;
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struct { unsigned int r[13]; } arm_regs;
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struct { unsigned int g[8], o[8], l[8], i[8]; } sparc_regs;
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struct { unsigned int g[8], o[8], l[8], i[8]; } sparc_regs;
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} integer; /* selected by SERVER_CTX_INTEGER */
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} integer; /* selected by SERVER_CTX_INTEGER */
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union
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union
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@ -63,6 +63,8 @@ static const unsigned int supported_cpus = CPU_FLAG(CPU_ALPHA);
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static const unsigned int supported_cpus = CPU_FLAG(CPU_POWERPC);
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static const unsigned int supported_cpus = CPU_FLAG(CPU_POWERPC);
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#elif defined(__sparc__)
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#elif defined(__sparc__)
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static const unsigned int supported_cpus = CPU_FLAG(CPU_SPARC);
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static const unsigned int supported_cpus = CPU_FLAG(CPU_SPARC);
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#elif defined(__arm__)
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static const unsigned int supported_cpus = CPU_FLAG(CPU_ARM);
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#else
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#else
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#error Unsupported CPU
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#error Unsupported CPU
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#endif
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#endif
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@ -1000,6 +1002,7 @@ static unsigned int get_context_system_regs( enum cpu_type cpu )
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case CPU_x86_64: return SERVER_CTX_DEBUG_REGISTERS;
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case CPU_x86_64: return SERVER_CTX_DEBUG_REGISTERS;
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case CPU_ALPHA: return 0;
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case CPU_ALPHA: return 0;
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case CPU_POWERPC: return 0;
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case CPU_POWERPC: return 0;
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case CPU_ARM: return 0;
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case CPU_SPARC: return 0;
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case CPU_SPARC: return 0;
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}
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}
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return 0;
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return 0;
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@ -1033,6 +1036,9 @@ void break_thread( struct thread *thread )
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case CPU_SPARC:
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case CPU_SPARC:
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data.exception.address = thread->context->ctl.sparc_regs.pc;
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data.exception.address = thread->context->ctl.sparc_regs.pc;
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break;
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break;
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case CPU_ARM:
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data.exception.address = thread->context->ctl.arm_regs.pc;
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break;
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}
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}
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generate_debug_event( thread, EXCEPTION_DEBUG_EVENT, &data );
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generate_debug_event( thread, EXCEPTION_DEBUG_EVENT, &data );
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thread->debug_break = 0;
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thread->debug_break = 0;
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@ -569,6 +569,14 @@ static void dump_varargs_context( const char *prefix, data_size_t size )
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fprintf( stderr, ",fpscr=%g", ctx.fp.powerpc_regs.fpscr );
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fprintf( stderr, ",fpscr=%g", ctx.fp.powerpc_regs.fpscr );
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}
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}
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break;
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break;
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case CPU_ARM:
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if (ctx.flags & SERVER_CTX_CONTROL)
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fprintf( stderr, ",sp=%08x,lr=%08x,pc=%08x,cpsr=%08x",
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ctx.ctl.arm_regs.sp, ctx.ctl.arm_regs.lr,
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ctx.ctl.arm_regs.pc, ctx.ctl.arm_regs.cpsr );
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if (ctx.flags & SERVER_CTX_INTEGER)
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for (i = 0; i < 13; i++) fprintf( stderr, ",r%u=%08x", i, ctx.integer.arm_regs.r[i] );
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break;
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case CPU_SPARC:
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case CPU_SPARC:
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if (ctx.flags & SERVER_CTX_CONTROL)
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if (ctx.flags & SERVER_CTX_CONTROL)
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fprintf( stderr, ",psr=%08x,pc=%08x,npc=%08x,y=%08x,wim=%08x,tbr=%08x",
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fprintf( stderr, ",psr=%08x,pc=%08x,npc=%08x,y=%08x,wim=%08x,tbr=%08x",
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