From 338f5e9cb6d6863ed3269deee93c4af664b321e0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Andr=C3=A9=20Hentschel?= <nerv@dawncrow.de>
Date: Sat, 7 Jul 2012 15:16:50 +0200
Subject: [PATCH] winedbg: Add new operators regarding data processing to ARM
 disassembler.

---
 programs/winedbg/be_arm.c | 54 +++++++++++++++++++++++++++++++++------
 1 file changed, 46 insertions(+), 8 deletions(-)

diff --git a/programs/winedbg/be_arm.c b/programs/winedbg/be_arm.c
index 709520810c0..1362ef18a2d 100644
--- a/programs/winedbg/be_arm.c
+++ b/programs/winedbg/be_arm.c
@@ -178,6 +178,48 @@ static UINT arm_disasm_branchxchg(UINT inst, ADDRESS64 *addr)
     return 0;
 }
 
+static UINT arm_disasm_mrstrans(UINT inst, ADDRESS64 *addr)
+{
+    short src = (inst >> 22) & 0x01;
+
+    dbg_printf("\n\tmrs%s\t%s, %s", get_cond(inst), tbl_regs[get_nibble(inst, 3)],
+               src ? "spsr" : "cpsr");
+    return 0;
+}
+
+static UINT arm_disasm_msrtrans(UINT inst, ADDRESS64 *addr)
+{
+    short immediate = (inst >> 25) & 0x01;
+    short dst = (inst >> 22) & 0x01;
+    short simple = (inst >> 16) & 0x01;
+
+    if (simple || !immediate)
+    {
+        dbg_printf("\n\tmsr%s\t%s, %s", get_cond(inst), dst ? "spsr" : "cpsr",
+                   tbl_regs[get_nibble(inst, 0)]);
+        return 0;
+    }
+
+    dbg_printf("\n\tmsr%s\t%s, #%u", get_cond(inst), dst ? "spsr" : "cpsr",
+               ROR32(inst & 0xff, 2 * get_nibble(inst, 2)));
+    return 0;
+}
+
+static UINT arm_disasm_wordmov(UINT inst, ADDRESS64 *addr)
+{
+    short top = (inst >> 22) & 0x01;
+
+    dbg_printf("\n\tmov%s%s\t%s, #%u", top ? "t" : "w", get_cond(inst),
+               tbl_regs[get_nibble(inst, 3)], (get_nibble(inst, 4) << 12) | (inst & 0x0fff));
+    return 0;
+}
+
+static UINT arm_disasm_nop(UINT inst, ADDRESS64 *addr)
+{
+    dbg_printf("\n\tnop%s", get_cond(inst));
+    return 0;
+}
+
 static UINT arm_disasm_dataprocessing(UINT inst, ADDRESS64 *addr)
 {
     short condcodes = (inst >> 20) & 0x01;
@@ -186,14 +228,6 @@ static UINT arm_disasm_dataprocessing(UINT inst, ADDRESS64 *addr)
     short no_op1    = (opcode & 0x0d) == 0x0d;
     short no_dst    = (opcode & 0x0c) == 0x08;
 
-    /* check for nop */
-    if (get_nibble(inst, 3) == 15 /* r15 */ && condcodes == 0 &&
-        opcode >= 8 /* tst */ && opcode <= 11 /* cmn */)
-    {
-        dbg_printf("\n\tnop");
-        return 0;
-    }
-
     dbg_printf("\n\t%s%s%s", tbl_dataops[opcode], condcodes ? "s" : "", get_cond(inst));
     if (!no_dst) dbg_printf("\t%s, ", tbl_regs[get_nibble(inst, 3)]);
     else dbg_printf("\t");
@@ -741,6 +775,10 @@ static const struct inst_arm tbl_arm[] = {
     { 0x0e000090, 0x00000090, arm_disasm_halfwordtrans },
     { 0x0ffffff0, 0x012fff00, arm_disasm_branchreg },
     { 0x0ffffff0, 0x012fff10, arm_disasm_branchxchg },
+    { 0x0fbf0fff, 0x010f0000, arm_disasm_mrstrans },
+    { 0x0dbef000, 0x0128f000, arm_disasm_msrtrans },
+    { 0x0fb00000, 0x03000000, arm_disasm_wordmov },
+    { 0x0fffffff, 0x0320f000, arm_disasm_nop },
     { 0x0c000000, 0x00000000, arm_disasm_dataprocessing },
     { 0x0c000000, 0x04000000, arm_disasm_singletrans },
     { 0x0e000000, 0x08000000, arm_disasm_blocktrans },