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winedbg: Add shifted register dataprocessing operators to Thumb2 disassembler.
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da817d8e91
commit
2b9555fba8
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@ -1206,6 +1206,100 @@ static UINT thumb2_disasm_dataprocessingmod(UINT inst, ADDRESS64 *addr)
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}
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}
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static UINT thumb2_disasm_dataprocessingshift(UINT inst, ADDRESS64 *addr)
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{
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WORD op = (inst >> 21) & 0x0f;
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WORD sf = (inst >> 20) & 0x01;
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WORD imm5 = ((inst >> 10) & 0x1c) + ((inst >> 6) & 0x03);
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WORD type = (inst >> 4) & 0x03;
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if (!imm5 && (type == 1 || type == 2)) imm5 = 32;
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else if (!imm5 && type == 3) type = 4;
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switch (op)
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{
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case 0:
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if (get_nibble(inst, 2) == 15)
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dbg_printf("\n\ttst\t%s, %s", tbl_regs[get_nibble(inst, 4)],
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tbl_regs[get_nibble(inst, 0)]);
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else
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dbg_printf("\n\tand%s\t%s, %s, %s", sf ? "s" : "", tbl_regs[get_nibble(inst, 2)],
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tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
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break;
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case 1:
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dbg_printf("\n\tbic%s\t%s, %s, %s", sf ? "s" : "", tbl_regs[get_nibble(inst, 2)],
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tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
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break;
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case 2:
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if (get_nibble(inst, 4) == 15)
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{
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if (type == 4)
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dbg_printf("\n\trrx%s\t%s, %s", sf ? "s" : "", tbl_regs[get_nibble(inst, 2)], tbl_regs[get_nibble(inst, 0)]);
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else if (!type && !imm5)
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dbg_printf("\n\tmov%s\t%s, %s", sf ? "s" : "", tbl_regs[get_nibble(inst, 2)], tbl_regs[get_nibble(inst, 0)]);
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else
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dbg_printf("\n\t%s%s\t%s, %s, #%u", tbl_shifts[type], sf ? "s" : "", tbl_regs[get_nibble(inst, 2)], tbl_regs[get_nibble(inst, 0)], imm5);
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return 0;
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}
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else
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dbg_printf("\n\torr%s\t%s, %s, %s", sf ? "s" : "", tbl_regs[get_nibble(inst, 2)],
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tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
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break;
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case 3:
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if (get_nibble(inst, 4) == 15)
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dbg_printf("\n\tmvn%s\t%s, %s, %s", sf ? "s" : "", tbl_regs[get_nibble(inst, 2)],
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tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
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else
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dbg_printf("\n\torn%s\t%s, %s, %s", sf ? "s" : "", tbl_regs[get_nibble(inst, 2)],
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tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
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break;
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case 4:
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if (get_nibble(inst, 2) == 15)
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dbg_printf("\n\tteq\t%s, %s", tbl_regs[get_nibble(inst, 4)],
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tbl_regs[get_nibble(inst, 0)]);
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else
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dbg_printf("\n\teor%s\t%s, %s, %s", sf ? "s" : "", tbl_regs[get_nibble(inst, 2)],
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tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
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break;
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case 8:
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if (get_nibble(inst, 2) == 15)
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dbg_printf("\n\tcmn\t%s, %s", tbl_regs[get_nibble(inst, 4)],
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tbl_regs[get_nibble(inst, 0)]);
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else
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dbg_printf("\n\tadd%s\t%s, %s, %s", sf ? "s" : "", tbl_regs[get_nibble(inst, 2)],
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tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
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break;
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case 10:
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dbg_printf("\n\tadc%s\t%s, %s, %s", sf ? "s" : "", tbl_regs[get_nibble(inst, 2)],
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tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
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break;
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case 11:
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dbg_printf("\n\tsbc%s\t%s, %s, %s", sf ? "s" : "", tbl_regs[get_nibble(inst, 2)],
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tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
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break;
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case 13:
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if (get_nibble(inst, 2) == 15)
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dbg_printf("\n\tcmp\t%s, %s", tbl_regs[get_nibble(inst, 4)],
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tbl_regs[get_nibble(inst, 0)]);
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else
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dbg_printf("\n\tsub%s\t%s, %s, %s", sf ? "s" : "", tbl_regs[get_nibble(inst, 2)],
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tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
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break;
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case 14:
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dbg_printf("\n\trsb%s\t%s, %s, %s", sf ? "s" : "", tbl_regs[get_nibble(inst, 2)],
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tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
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break;
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default:
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return inst;
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}
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if (type == 4)
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dbg_printf(", rrx");
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else if (type || imm5)
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dbg_printf(", %s #%u", tbl_shifts[type], imm5);
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return 0;
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}
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static UINT thumb2_disasm_coprocdat(UINT inst, ADDRESS64 *addr)
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{
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WORD opc2 = (inst >> 5) & 0x07;
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@ -1444,6 +1538,7 @@ static const struct inst_arm tbl_thumb32[] = {
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{ 0xfe500000, 0xf8100000, thumb2_disasm_ldrnonword },
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{ 0xfa008000, 0xf2000000, thumb2_disasm_dataprocessing },
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{ 0xfa008000, 0xf0000000, thumb2_disasm_dataprocessingmod },
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{ 0xfe008000, 0xea000000, thumb2_disasm_dataprocessingshift },
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{ 0xef000010, 0xee000000, thumb2_disasm_coprocdat },
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{ 0xef000010, 0xee000010, thumb2_disasm_coprocmov1 },
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{ 0xefe00000, 0xec400000, thumb2_disasm_coprocmov2 },
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