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c99a3efc5b
Some of these don't just use the REG bits of the mod/rm byte as slashes, but also the R/M bits to have up to 9 different instructions per opcode/slash combination (1 opcode requires that MOD is != 11, the other 8 have MODE == 11). This is done by making the slashes table two levels deep for these cases. Some of this is cosmetic (e.g "FST st0" has no effect already, but its bit pattern gets disassembled as "FNOP"), but for most uses it isn't. FSTENV and FSTCW have an extraordinary 0x9b prefix. This is not yet handled in this patch. |
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| .. | ||
| CMakeLists.txt | ||
| Emulator.cpp | ||
| Emulator.h | ||
| main.cpp | ||
| MallocTracer.cpp | ||
| MallocTracer.h | ||
| MmapRegion.cpp | ||
| MmapRegion.h | ||
| SharedBufferRegion.cpp | ||
| SharedBufferRegion.h | ||
| SimpleRegion.cpp | ||
| SimpleRegion.h | ||
| SoftCPU.cpp | ||
| SoftCPU.h | ||
| SoftMMU.cpp | ||
| SoftMMU.h | ||
| ValueWithShadow.h | ||