mirror of
https://github.com/SerenityOS/serenity
synced 2024-07-24 11:35:13 +00:00
982ce17927
Prekernel code currently assumes that mapping until MAX_KERNEL_SIZE is enough to make the modules accessible. GRUB tries to load as low as possible but higher than 1 MiB. Hence this is usually true. However on EFI some ranges may already be used by boot services and GRUB tries to avoid them if possible. This pushes modules higher. The simplest solution is to map entire 4 GiB space. As an additional benefit it makes the framebuffer accessible that can be used for the debugging.
655 lines
14 KiB
ArmAsm
655 lines
14 KiB
ArmAsm
#include <AK/Platform.h>
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#include <Kernel/Prekernel/Prekernel.h>
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.code32
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.section .stack, "aw", @nobits
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stack_bottom:
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.skip 32768
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stack_top:
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.global kernel_cmdline
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kernel_cmdline:
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.skip 4096
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.section .page_tables, "aw", @nobits
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.align 4096
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#if ARCH(X86_64)
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.global boot_pml4t
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boot_pml4t:
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.skip 4096
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#endif
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.global boot_pdpt
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boot_pdpt:
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.skip 4096
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.global boot_pd0
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boot_pd0:
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.skip (4096 * 4)
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.global boot_pd0_pts
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boot_pd0_pts:
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.skip 4096 * (MAX_KERNEL_SIZE >> 21)
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.global boot_pd_kernel
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boot_pd_kernel:
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.skip 4096
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.global boot_pd_kernel_pt0
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boot_pd_kernel_pt0:
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.skip 4096
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.global boot_pd_kernel_image_pts
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boot_pd_kernel_image_pts:
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.skip 4096 * (MAX_KERNEL_SIZE >> 21)
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.global boot_pd_kernel_pt1023
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boot_pd_kernel_pt1023:
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.skip 4096
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.section .text
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.global start
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.type start, @function
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.extern init
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.type init, @function
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.global reload_cr3
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.type reload_cr3, @function
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.extern multiboot_info_ptr
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.type multiboot_info_ptr, @object
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/*
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construct the following (64-bit PML4T) page table layout:
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(the PML4T part is not used for 32-bit x86)
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pml4t:
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0: pdpt (0-512GB)
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pdpt
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0: boot_pd0 (0-1GB)
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1: boot_pd0 + 4096 (1-2GB)
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2: boot_pd0 + 4096 * 2 (2-3GB)
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3: boot_pd0 + 4096 * 3 (3-4GB)
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boot_pd0 : 512 PDEs
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boot_pd0_pts (0MB - MAX_KERNEL_SIZE) (id 512 4KB pages)
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the page tables each contain 512 PTEs that map individual 4KB pages
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*/
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gdt64:
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.quad 0
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gdt64code:
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.quad (1<<43) | (1<<44) | (1<<47) | (1<<53) /* executable, code segment, present, 64-bit */
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.global gdt64ptr
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gdt64ptr:
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.short . - gdt64 - 1
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.quad gdt64
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.set code64_sel_value, gdt64code - gdt64
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.global code64_sel
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code64_sel:
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.short code64_sel_value
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start:
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jmp real_start
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/*
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param 1: pointer to C string
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returns: Length of string (including null byte)
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*/
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print_no_halt:
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pushl %ebp
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movl %esp, %ebp
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pushl %esi
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pushl %ecx
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movl 8(%ebp), %esi
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mov $0xb8000, %ecx /* VRAM address. */
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mov $0x07, %ah /* grey-on-black text. */
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.Lprint_str_loop:
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lodsb /* Loads a byte from address at %esi into %al and increments %esi. */
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test %al, %al
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jz .Lprint_str_end
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movw %ax, (%ecx)
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add $2, %ecx
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jmp .Lprint_str_loop
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.Lprint_str_end:
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mov %esi, %eax
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sub 8(%ebp), %eax
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popl %ecx
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popl %esi
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movl %ebp, %esp
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popl %ebp
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ret
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/*
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this function assumes that paging is disabled (or everything is mapped 1:1)
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param 1: pointer to string ended with null terminator (C string)
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*/
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print_and_halt:
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/* from now on, we don't really care about booting because we are missing required CPU features such as PAE or long mode.
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the flow from now is like so:
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1. Copy all necessary parts to low memory section in RAM
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2. Jump to that section
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3. In that section we do:
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a. exit protected mode to pure 16 bit real mode
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b. load the "<missing feature> is not supported" String, call the BIOS print to screen service
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c. halt
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*/
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.equ COPIED_STRING_LOCATION, 0x400
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.equ GDT_REAL_MODE_LOCATION, 0x45000
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.equ EXITING_PROTECTED_MODE_CODE_LOCATION, 0x10000
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.equ REAL_MODE_CODE, 0x500
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.equ PROTECTED_MODE_16_BIT_CODE, 0x600
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movl %esp, %ebp
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movl 4(%ebp), %esi
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/* Print string using non-destructive methods */
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pushl %esi
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call print_no_halt
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addl $4, %esp
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/* print_no_halt returns the string length (including null byte) in eax. */
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mov %eax, %ecx
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movw %cx, (COPIED_STRING_LOCATION) /* Store string length for later use. */
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/* Copy string into lower memory */
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mov 4(%ebp), %esi
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mov $COPIED_STRING_LOCATION + 2, %edi
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rep movsb
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/* Copy gdt_table_real_mode to low memory section */
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movl $gdt_table_real_mode, %eax
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movl $gdt_table_real_mode_end, %ebx
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movl %ebx, %ecx
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sub %eax, %ecx
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mov %eax, %esi /* source address of the code */
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mov $GDT_REAL_MODE_LOCATION, %edi /* destination address of the code */
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rep movsb
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/* Copy protected_mode_16_bit to real_mode to low memory section */
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movl $protected_mode_16_bit, %eax
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movl $real_mode, %ebx
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movl %ebx, %ecx
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sub %eax, %ecx
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mov %eax, %esi /* source address of the code */
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mov $PROTECTED_MODE_16_BIT_CODE, %edi /* destination address of the code */
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rep movsb
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/* Copy real_mode to end_of_print_and_halt_function to low memory section */
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movl $real_mode, %eax
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movl $end_of_print_and_halt_function, %ebx
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movl %ebx, %ecx
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sub %eax, %ecx
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mov %eax, %esi /* source address of the code */
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mov $REAL_MODE_CODE, %edi /* destination address of the code */
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rep movsb
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/* Copy all opcodes from exiting_real_mode label to protected_mode_16_bit label to low memory RAM */
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movl $exiting_real_mode, %eax
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movl $protected_mode_16_bit, %ebx
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movl %ebx, %ecx
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sub %eax, %ecx
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mov %eax, %esi /* source address of the code */
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mov $EXITING_PROTECTED_MODE_CODE_LOCATION, %edi /* destination address of the code */
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pushl %edi
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rep movsb
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popl %edi
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pushl %edi
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ret
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gdt_table_real_mode:
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.quad 0 /* Empty entry */
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.short 0xffff
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.short 0
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.byte 0
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.byte 0b10011010
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.byte 0b00001111
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.byte 0x0
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.short 0xffff
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.short 0
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.byte 0
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.byte 0b10010010
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.byte 0b00001111
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.byte 0x0
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gdt_table_real_mode_end:
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no_long_mode_string:
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.asciz "Your computer does not support long mode (64-bit mode). Halting!"
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no_pae_string:
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.asciz "Your computer does not support PAE. Halting!"
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pentium_m_forcepae_string:
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.asciz "Intel Pentium M detected. Assuming present but unadvertised PAE support."
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kernel_image_too_big_string:
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.asciz "Error: Kernel Image too big for memory slot. Halting!"
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/*
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This part is completely standalone - it doesn't involve any location from this
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near code. It uses arbitrary locations in the low memory section of the RAM.
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We don't really worry about where are these locations, because we only want to quickly
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print a string and halt.
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*/
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.code32
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exiting_real_mode:
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/* Build IDT pointer and load it */
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mov $0x50000, %eax
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pushl %eax
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movl $0x3ff, 0(%eax)
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add $2, %eax
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movl $0, 0(%eax)
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popl %eax
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lidt (%eax)
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/* Build GDT pointer and load it */
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mov $0x40000, %eax
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pushl %eax
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movl $32, 0(%eax)
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add $2, %eax
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movl $GDT_REAL_MODE_LOCATION, 0(%eax)
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popl %eax
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lgdt (%eax)
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/* far jump to protected_mode_16_bit in 0x5000 */
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pushw $8
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push $PROTECTED_MODE_16_BIT_CODE
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lret
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hlt
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.code16
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protected_mode_16_bit:
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xor %eax, %eax
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movl $0x10, %eax
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movw %ax, %ds
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and $0xFE, %al /* switch to pure real mode */
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mov %eax, %cr0
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mov $0x10, %eax
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movl %eax, %cr0
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pushw $0
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push $REAL_MODE_CODE
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lret
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hlt
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real_mode:
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movw $0x7000, %ax
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movl $0x0000, %esp
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movw %ax, %ss
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xor %ax, %ax
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movw %ax, %ds
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movw %ax, %es
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movw %ax, %fs
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movw %ax, %gs
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mov $0x3, %ax
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int $0x10
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movb $0x13, %ah
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movb $0x0, %bh
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movb $0xf, %bl
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movw (COPIED_STRING_LOCATION), %cx
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movw $0, %dx
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movw $COPIED_STRING_LOCATION + 2, %bp
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int $0x10
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movl $0xdeadcafe, %ebx
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cli
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hlt
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end_of_print_and_halt_function:
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.code32
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real_start:
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cli
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cld
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mov $end_of_prekernel_image, %esi
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cmp $MAX_KERNEL_SIZE, %esi
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jbe kernel_not_too_large
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movl $kernel_image_too_big_string, %esi
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pushl %esi
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call print_and_halt
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/* We should not return, but just in case, halt */
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hlt
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kernel_not_too_large:
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/* test for PAE presence, save the most important registers from corruption */
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pushl %eax
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pushl %edx
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pushl %ebx
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movl $0x1, %eax /* PAE presence is in CPUID input 0x1 */
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cpuid
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testl $(1 << 6), %edx /* Test if the PAE-bit, which is bit 6, is set in the edx register. */
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jnz pae_supported /* If the bit is not set, there is no PAE capability. */
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/* We might have a Pentium M, which supports PAE but doesn't advertise it. */
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call is_pentium_m_with_hidden_pae
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test %eax, %eax
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jz .Lskip_forcepae
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/* Print a warning message, but continue. */
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pushl $pentium_m_forcepae_string
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call print_no_halt
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subl $4, %esp
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jmp pae_supported
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.Lskip_forcepae:
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/* Since there is no PAE capability, halt with an error message */
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movl $no_pae_string, %esi
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pushl %esi
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call print_and_halt
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/* We should not return, but just in case, halt */
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hlt
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pae_supported:
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movl $0x80000001, %eax
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cpuid
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testl $(1 << 29), %edx /* Test if the LM-bit, which is bit 29, is set in the edx register. */
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jnz long_mode_supported /* If LM-bit is not enabled, there is no long mode. */
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/* Since there is no long mode, halt with an error message */
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movl $no_long_mode_string, %esi
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pushl %esi
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call print_and_halt
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/* We should not return, but just in case, halt */
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hlt
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/* If both PAE and long mode is supported, continue with booting the system */
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long_mode_supported:
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/* restore the pushed registers and continue with booting */
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popl %ebx
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popl %edx
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popl %eax
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/* We don't know where the bootloader might have put the command line.
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* It might be at an inconvenient location that we're not about to map,
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* so let's just copy it to a convenient location while we have the whole
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* memory space identity-mapped anyway. :^)
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*/
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movl %ebx, %esi
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addl $16, %esi
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movl (%esi), %esi
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movl $1024, %ecx
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movl $kernel_cmdline, %edi
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rep movsl
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/* clear pml4t */
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movl $boot_pml4t, %edi
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movl $1024, %ecx
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xorl %eax, %eax
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rep stosl
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/* set up pml4t[0] */
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movl $boot_pml4t, %edi
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movl $boot_pdpt, 0(%edi)
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/* R/W + Present */
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orl $0x3, 0(%edi)
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/* clear pdpt */
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movl $boot_pdpt, %edi
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movl $1024, %ecx
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xorl %eax, %eax
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rep stosl
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/* set up pdpt[0]..pdpt[3] */
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movl $boot_pdpt, %edi
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movl $(boot_pd0 + 3), 0(%edi)
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movl $(boot_pd0 + 4096 + 3), 8(%edi)
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movl $(boot_pd0 + 4096 * 2 + 3), 16(%edi)
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movl $(boot_pd0 + 4096 * 3 + 3), 24(%edi)
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/* clear pd0 */
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movl $boot_pd0, %edi
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movl $4096, %ecx
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xorl %eax, %eax
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rep stosl
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/* clear pd0's PTs */
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movl $boot_pd0_pts, %edi
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movl $(1024 * (MAX_KERNEL_SIZE >> 21)), %ecx
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xorl %eax, %eax
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rep stosl
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/* add boot_pd0_pts to boot_pd0 */
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movl $(MAX_KERNEL_SIZE >> 21), %ecx
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movl $boot_pd0, %edi
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movl $boot_pd0_pts, %eax
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1:
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movl %eax, 0(%edi)
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/* R/W + Present */
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orl $0x3, 0(%edi)
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addl $8, %edi
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addl $4096, %eax
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loop 1b
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/* identity map the 0MB to MAX_KERNEL_SIZE range */
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movl $(512 * (MAX_KERNEL_SIZE >> 21)), %ecx
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movl $boot_pd0_pts, %edi
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xorl %eax, %eax
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1:
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movl %eax, 0(%edi)
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/* R/W + Present */
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orl $0x3, 0(%edi)
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addl $8, %edi
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addl $4096, %eax
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loop 1b
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/* Map the rest with 2MiB pages */
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/* add boot_pd0_pts to boot_pd0 */
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movl $(2048 - (MAX_KERNEL_SIZE >> 21)), %ecx
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movl $(boot_pd0 + (MAX_KERNEL_SIZE >> 21) * 8), %edi
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/* R/W + Present + 2 MiB */
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movl $(MAX_KERNEL_SIZE | 0x83), %eax
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1:
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movl %eax, 0(%edi)
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addl $8, %edi
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addl $(1 << 21), %eax
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loop 1b
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/* point CR3 to PML4T */
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movl $boot_pml4t, %eax
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movl %eax, %cr3
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/* enable PAE + PSE */
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movl %cr4, %eax
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orl $0x60, %eax
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movl %eax, %cr4
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1:
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/* Enter Long-mode! ref(https://wiki.osdev.org/Setting_Up_Long_Mode)*/
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mov $0xC0000080, %ecx /* Set the C-register to 0xC0000080, which is the EFER MSR.*/
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rdmsr /* Read from the model-specific register.*/
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or $(1 << 8), %eax /* Set the LM-bit which is the 9th bit (bit 8).*/
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wrmsr /* Write to the model-specific register.*/
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/* enable PG */
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movl %cr0, %eax
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orl $0x80000000, %eax
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movl %eax, %cr0
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/* set up stack */
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mov $stack_top, %esp
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and $-16, %esp
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/* Now we are in 32-bit compatibility mode, We still need to load a 64-bit GDT */
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mov $gdt64ptr, %eax
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lgdt (%eax)
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ljmpl $code64_sel_value, $1f
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.code64
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1:
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movl %ebx, %ebx
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movq %rbx, multiboot_info_ptr
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mov $0, %ax
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mov %ax, %ss
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mov %ax, %ds
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mov %ax, %es
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mov %ax, %fs
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mov %ax, %gs
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call reload_cr3
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call init
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cli
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loop:
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hlt
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jmp loop
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reload_cr3:
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pushq %rax
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mov %cr3, %rax
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mov %rax, %cr3
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popq %rax
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ret
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.code32
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/* Determines if the CPU is made by Intel */
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is_intel_cpu:
|
|
pushl %ebp
|
|
movl %esp, %ebp
|
|
|
|
pushl %ebx
|
|
|
|
xorl %eax, %eax
|
|
cpuid
|
|
|
|
xorl %eax, %eax
|
|
cmpl $0x756e6547, %ebx /* "Genu" */
|
|
jnz .Lis_intel_cpu_end
|
|
cmpl $0x49656e69, %edx /* "ineI" */
|
|
jnz .Lis_intel_cpu_end
|
|
cmpl $0x6c65746e, %ecx /* "ntel" */
|
|
jnz .Lis_intel_cpu_end
|
|
|
|
movl $1, %eax
|
|
|
|
.Lis_intel_cpu_end:
|
|
popl %ebx
|
|
|
|
movl %ebp, %esp
|
|
popl %ebp
|
|
|
|
ret
|
|
|
|
/* Fetches the CPU family (eax) and model (edx) */
|
|
get_cpu_model_family:
|
|
pushl %ebp
|
|
movl %esp, %ebp
|
|
|
|
pushl %ebx
|
|
|
|
movl $0x1, %eax
|
|
cpuid
|
|
movl %eax, %ebx
|
|
movl %eax, %ecx
|
|
movl %eax, %edx
|
|
|
|
/* Bit 8 - 11: Processor Family */
|
|
shrl $8, %eax
|
|
andl $0xf, %eax
|
|
|
|
/* Bit 4 - 7: Processor Model */
|
|
shrl $4, %edx
|
|
andl $0xf, %edx
|
|
|
|
/* Bit 16 - 19: Extended Model ID */
|
|
/* (only applies if Family is 6 or 15) */
|
|
cmpl $6, %eax
|
|
jz .Ldo_ext_model
|
|
cmpl $15, %eax
|
|
jz .Ldo_ext_model
|
|
jmp .Lskip_ext_model
|
|
.Ldo_ext_model:
|
|
shrl $16, %ebx
|
|
andl $0xf, %ebx
|
|
shll $4, %ebx
|
|
addl %ebx, %edx
|
|
.Lskip_ext_model:
|
|
|
|
/* Bit 20 - 27: Extended Family */
|
|
/* (only applies if Family is 15) */
|
|
cmpl $15, %eax
|
|
jnz .Lskip_ext_family
|
|
shrl $20, %ecx
|
|
andl $0xff, %ecx
|
|
addl %ecx, %eax
|
|
.Lskip_ext_family:
|
|
|
|
popl %ebx
|
|
|
|
movl %ebp, %esp
|
|
popl %ebp
|
|
|
|
ret
|
|
|
|
/* Determines if the CPU is an Intel Pentium M with hidden PAE flag. */
|
|
is_pentium_m_with_hidden_pae:
|
|
pushl %ebp
|
|
movl %esp, %ebp
|
|
|
|
/* Check the manufacturer string. */
|
|
call is_intel_cpu
|
|
testl %eax, %eax
|
|
jz .Lis_pentium_m_end
|
|
|
|
/* Check the processor model. */
|
|
call get_cpu_model_family
|
|
movl %eax, %ecx /* Free up eax for the return value. */
|
|
xorl %eax, %eax
|
|
|
|
cmpl $6, %ecx /* Family 6: Big Cores */
|
|
jnz .Lis_pentium_m_end
|
|
|
|
cmpl $9, %edx /* Model 9: Pentium M (Banias) */
|
|
jz .Lpass_model_check
|
|
cmpl $13, %edx /* Model 13: Pentium M (Dothan) */
|
|
jz .Lpass_model_check
|
|
jmp .Lis_pentium_m_end
|
|
.Lpass_model_check:
|
|
|
|
/* We are a Pentium M. */
|
|
movl $1, %eax
|
|
|
|
.Lis_pentium_m_end:
|
|
movl %ebp, %esp
|
|
popl %ebp
|
|
|
|
ret
|