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https://github.com/SerenityOS/serenity
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d61c23569e
The VirtIO specification defines many types of devices with different purposes, and it also defines 3 possible transport mediums where devices could be connected to the host machine. We only care about the PCIe transport, but this commit puts the actual foundations for supporting the lean MMIO transport too in the future. To ensure things are kept abstracted but still functional, the VirtIO transport code is responsible for what is deemed as related to an actual transport type - allocation of interrupt handlers and tinkering with low level transport-related registers, etc.
77 lines
2 KiB
C++
77 lines
2 KiB
C++
/*
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* Copyright (c) 2021, the SerenityOS developers.
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#pragma once
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#include <AK/Types.h>
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namespace Kernel::VirtIO {
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#define REG_DEVICE_FEATURES 0x0
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#define REG_GUEST_FEATURES 0x4
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#define REG_QUEUE_ADDRESS 0x8
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#define REG_QUEUE_SIZE 0xc
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#define REG_QUEUE_SELECT 0xe
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#define REG_QUEUE_NOTIFY 0x10
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#define REG_DEVICE_STATUS 0x12
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#define REG_ISR_STATUS 0x13
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#define DEVICE_STATUS_ACKNOWLEDGE (1 << 0)
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#define DEVICE_STATUS_DRIVER (1 << 1)
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#define DEVICE_STATUS_DRIVER_OK (1 << 2)
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#define DEVICE_STATUS_FEATURES_OK (1 << 3)
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#define DEVICE_STATUS_DEVICE_NEEDS_RESET (1 << 6)
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#define DEVICE_STATUS_FAILED (1 << 7)
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#define VIRTIO_F_INDIRECT_DESC ((u64)1 << 28)
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#define VIRTIO_F_VERSION_1 ((u64)1 << 32)
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#define VIRTIO_F_RING_PACKED ((u64)1 << 34)
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#define VIRTIO_F_IN_ORDER ((u64)1 << 35)
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#define VIRTIO_PCI_CAP_COMMON_CFG 1
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#define VIRTIO_PCI_CAP_NOTIFY_CFG 2
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#define VIRTIO_PCI_CAP_ISR_CFG 3
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#define VIRTIO_PCI_CAP_DEVICE_CFG 4
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#define VIRTIO_PCI_CAP_PCI_CFG 5
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// virtio_pci_common_cfg
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#define COMMON_CFG_DEVICE_FEATURE_SELECT 0x0
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#define COMMON_CFG_DEVICE_FEATURE 0x4
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#define COMMON_CFG_DRIVER_FEATURE_SELECT 0x8
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#define COMMON_CFG_DRIVER_FEATURE 0xc
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#define COMMON_CFG_MSIX_CONFIG 0x10
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#define COMMON_CFG_NUM_QUEUES 0x12
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#define COMMON_CFG_DEVICE_STATUS 0x14
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#define COMMON_CFG_CONFIG_GENERATION 0x15
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#define COMMON_CFG_QUEUE_SELECT 0x16
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#define COMMON_CFG_QUEUE_SIZE 0x18
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#define COMMON_CFG_QUEUE_MSIX_VECTOR 0x1a
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#define COMMON_CFG_QUEUE_ENABLE 0x1c
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#define COMMON_CFG_QUEUE_NOTIFY_OFF 0x1e
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#define COMMON_CFG_QUEUE_DESC 0x20
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#define COMMON_CFG_QUEUE_DRIVER 0x28
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#define COMMON_CFG_QUEUE_DEVICE 0x30
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#define QUEUE_INTERRUPT 0x1
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#define DEVICE_CONFIG_INTERRUPT 0x2
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enum class ConfigurationType : u8 {
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Common = 1,
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Notify = 2,
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ISR = 3,
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Device = 4,
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PCICapabilitiesAccess = 5
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};
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struct Configuration {
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ConfigurationType cfg_type;
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u8 resource_index; // NOTE: For PCI devices, this is the BAR index
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u32 offset;
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u32 length;
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};
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}
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