mirror of
https://github.com/SerenityOS/serenity
synced 2024-10-19 06:12:52 +00:00
5b7f8634e3
Since the kernel page tables are shared between all processes, there's no need to (implicitly) flush the TLB for them on every context switch. Setting the G bit on kernel page tables allows the CPU to keep the translation caches around.
480 lines
11 KiB
C++
480 lines
11 KiB
C++
#pragma once
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#include <AK/Badge.h>
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#include <AK/Noncopyable.h>
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#include <Kernel/VM/VirtualAddress.h>
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#include <Kernel/kstdio.h>
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#define PAGE_SIZE 4096
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#define PAGE_MASK 0xfffff000
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class MemoryManager;
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class PageTableEntry;
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struct [[gnu::packed]] TSS32
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{
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u16 backlink, __blh;
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u32 esp0;
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u16 ss0, __ss0h;
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u32 esp1;
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u16 ss1, __ss1h;
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u32 esp2;
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u16 ss2, __ss2h;
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u32 cr3, eip, eflags;
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u32 eax, ecx, edx, ebx, esp, ebp, esi, edi;
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u16 es, __esh;
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u16 cs, __csh;
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u16 ss, __ssh;
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u16 ds, __dsh;
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u16 fs, __fsh;
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u16 gs, __gsh;
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u16 ldt, __ldth;
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u16 trace, iomapbase;
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};
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union [[gnu::packed]] Descriptor
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{
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struct {
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u16 limit_lo;
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u16 base_lo;
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u8 base_hi;
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u8 type : 4;
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u8 descriptor_type : 1;
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u8 dpl : 2;
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u8 segment_present : 1;
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u8 limit_hi : 4;
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u8 : 1;
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u8 zero : 1;
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u8 operation_size : 1;
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u8 granularity : 1;
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u8 base_hi2;
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};
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struct {
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u32 low;
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u32 high;
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};
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enum Type {
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Invalid = 0,
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AvailableTSS_16bit = 0x1,
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LDT = 0x2,
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BusyTSS_16bit = 0x3,
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CallGate_16bit = 0x4,
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TaskGate = 0x5,
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InterruptGate_16bit = 0x6,
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TrapGate_16bit = 0x7,
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AvailableTSS_32bit = 0x9,
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BusyTSS_32bit = 0xb,
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CallGate_32bit = 0xc,
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InterruptGate_32bit = 0xe,
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TrapGate_32bit = 0xf,
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};
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void set_base(void* b)
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{
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base_lo = (u32)(b)&0xffff;
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base_hi = ((u32)(b) >> 16) & 0xff;
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base_hi2 = ((u32)(b) >> 24) & 0xff;
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}
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void set_limit(u32 l)
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{
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limit_lo = (u32)l & 0xffff;
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limit_hi = ((u32)l >> 16) & 0xff;
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}
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};
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class PageDirectoryEntry {
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AK_MAKE_NONCOPYABLE(PageDirectoryEntry);
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public:
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PageTableEntry* page_table_base() { return reinterpret_cast<PageTableEntry*>(m_raw & 0xfffff000u); }
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void set_page_table_base(u32 value)
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{
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m_raw &= 0xfff;
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m_raw |= value & 0xfffff000;
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}
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u32 raw() const { return m_raw; }
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void copy_from(Badge<MemoryManager>, const PageDirectoryEntry& other) { m_raw = other.m_raw; }
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enum Flags {
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Present = 1 << 0,
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ReadWrite = 1 << 1,
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UserSupervisor = 1 << 2,
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WriteThrough = 1 << 3,
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CacheDisabled = 1 << 4,
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Global = 1 << 8,
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};
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bool is_present() const { return raw() & Present; }
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void set_present(bool b) { set_bit(Present, b); }
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bool is_user_allowed() const { return raw() & UserSupervisor; }
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void set_user_allowed(bool b) { set_bit(UserSupervisor, b); }
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bool is_writable() const { return raw() & ReadWrite; }
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void set_writable(bool b) { set_bit(ReadWrite, b); }
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bool is_write_through() const { return raw() & WriteThrough; }
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void set_write_through(bool b) { set_bit(WriteThrough, b); }
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bool is_cache_disabled() const { return raw() & CacheDisabled; }
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void set_cache_disabled(bool b) { set_bit(CacheDisabled, b); }
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bool is_global() const { return raw() & Global; }
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void set_global(bool b) { set_bit(Global, b); }
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void set_bit(u32 bit, bool value)
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{
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if (value)
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m_raw |= bit;
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else
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m_raw &= ~bit;
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}
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private:
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u32 m_raw;
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};
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class PageTableEntry {
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AK_MAKE_NONCOPYABLE(PageTableEntry);
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public:
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void* physical_page_base() { return reinterpret_cast<void*>(m_raw & 0xfffff000u); }
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void set_physical_page_base(u32 value)
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{
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m_raw &= 0xfff;
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m_raw |= value & 0xfffff000;
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}
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u32 raw() const { return m_raw; }
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enum Flags {
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Present = 1 << 0,
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ReadWrite = 1 << 1,
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UserSupervisor = 1 << 2,
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WriteThrough = 1 << 3,
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CacheDisabled = 1 << 4,
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Global = 1 << 8,
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};
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bool is_present() const { return raw() & Present; }
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void set_present(bool b) { set_bit(Present, b); }
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bool is_user_allowed() const { return raw() & UserSupervisor; }
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void set_user_allowed(bool b) { set_bit(UserSupervisor, b); }
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bool is_writable() const { return raw() & ReadWrite; }
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void set_writable(bool b) { set_bit(ReadWrite, b); }
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bool is_write_through() const { return raw() & WriteThrough; }
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void set_write_through(bool b) { set_bit(WriteThrough, b); }
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bool is_cache_disabled() const { return raw() & CacheDisabled; }
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void set_cache_disabled(bool b) { set_bit(CacheDisabled, b); }
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bool is_global() const { return raw() & Global; }
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void set_global(bool b) { set_bit(Global, b); }
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void set_bit(u32 bit, bool value)
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{
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if (value)
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m_raw |= bit;
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else
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m_raw &= ~bit;
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}
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private:
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u32 m_raw;
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};
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static_assert(sizeof(PageDirectoryEntry) == 4);
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static_assert(sizeof(PageTableEntry) == 4);
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class IRQHandler;
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void gdt_init();
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void idt_init();
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void sse_init();
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void register_interrupt_handler(u8 number, void (*f)());
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void register_user_callable_interrupt_handler(u8 number, void (*f)());
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void register_irq_handler(u8 number, IRQHandler&);
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void unregister_irq_handler(u8 number, IRQHandler&);
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void flush_idt();
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void flush_gdt();
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void load_task_register(u16 selector);
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u16 gdt_alloc_entry();
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void gdt_free_entry(u16);
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Descriptor& get_gdt_entry(u16 selector);
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void write_gdt_entry(u16 selector, Descriptor&);
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[[noreturn]] static inline void hang()
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{
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asm volatile("cli; hlt");
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for (;;) {
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}
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}
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#define LSW(x) ((u32)(x)&0xFFFF)
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#define MSW(x) (((u32)(x) >> 16) & 0xFFFF)
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#define LSB(x) ((x)&0xFF)
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#define MSB(x) (((x) >> 8) & 0xFF)
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#define cli() asm volatile("cli" :: \
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: "memory")
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#define sti() asm volatile("sti" :: \
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: "memory")
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#define memory_barrier() asm volatile("" :: \
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: "memory")
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inline u32 cpu_cr3()
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{
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u32 cr3;
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asm volatile("movl %%cr3, %%eax"
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: "=a"(cr3));
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return cr3;
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}
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inline u32 cpu_flags()
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{
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u32 flags;
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asm volatile(
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"pushf\n"
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"pop %0\n"
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: "=rm"(flags)::"memory");
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return flags;
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}
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inline u32 read_fs_u32(u32 offset)
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{
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u32 val;
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asm volatile(
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"movl %%fs:%a[off], %k[val]"
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: [val] "=r" (val)
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: [off] "ir" (offset));
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return val;
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}
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inline void write_fs_u32(u32 offset, u32 val)
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{
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asm volatile(
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"movl %k[val], %%fs:%a[off]"
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:: [off] "ir" (offset), [val] "ir" (val)
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: "memory");
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}
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inline bool are_interrupts_enabled()
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{
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return cpu_flags() & 0x200;
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}
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class InterruptFlagSaver {
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public:
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InterruptFlagSaver()
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{
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m_flags = cpu_flags();
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}
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~InterruptFlagSaver()
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{
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if (m_flags & 0x200)
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sti();
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else
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cli();
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}
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private:
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u32 m_flags;
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};
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class InterruptDisabler {
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public:
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InterruptDisabler()
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{
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m_flags = cpu_flags();
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cli();
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}
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~InterruptDisabler()
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{
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if (m_flags & 0x200)
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sti();
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}
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private:
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u32 m_flags;
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};
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/* Map IRQ0-15 @ ISR 0x50-0x5F */
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#define IRQ_VECTOR_BASE 0x50
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struct PageFaultFlags {
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enum Flags {
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NotPresent = 0x00,
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ProtectionViolation = 0x01,
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Read = 0x00,
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Write = 0x02,
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UserMode = 0x04,
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SupervisorMode = 0x00,
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InstructionFetch = 0x08,
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};
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};
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class PageFault {
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public:
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PageFault(u16 code, VirtualAddress vaddr)
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: m_code(code)
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, m_vaddr(vaddr)
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{
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}
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enum class Type {
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PageNotPresent = PageFaultFlags::NotPresent,
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ProtectionViolation = PageFaultFlags::ProtectionViolation,
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};
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enum class Access {
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Read = PageFaultFlags::Read,
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Write = PageFaultFlags::Write,
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};
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VirtualAddress vaddr() const { return m_vaddr; }
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u16 code() const { return m_code; }
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Type type() const { return (Type)(m_code & 1); }
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Access access() const { return (Access)(m_code & 2); }
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bool is_not_present() const { return (m_code & 1) == PageFaultFlags::NotPresent; }
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bool is_protection_violation() const { return (m_code & 1) == PageFaultFlags::ProtectionViolation; }
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bool is_read() const { return (m_code & 2) == PageFaultFlags::Read; }
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bool is_write() const { return (m_code & 2) == PageFaultFlags::Write; }
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bool is_user() const { return (m_code & 4) == PageFaultFlags::UserMode; }
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bool is_supervisor() const { return (m_code & 4) == PageFaultFlags::SupervisorMode; }
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bool is_instruction_fetch() const { return (m_code & 8) == PageFaultFlags::InstructionFetch; }
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private:
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u16 m_code;
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VirtualAddress m_vaddr;
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};
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struct [[gnu::packed]] RegisterDump
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{
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u16 ss;
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u16 gs;
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u16 fs;
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u16 es;
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u16 ds;
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u32 edi;
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u32 esi;
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u32 ebp;
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u32 esp;
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u32 ebx;
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u32 edx;
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u32 ecx;
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u32 eax;
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u16 exception_code;
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u16 __exception_code_padding;
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u32 eip;
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u16 cs;
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u16 __csPadding;
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u32 eflags;
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u32 esp_if_crossRing;
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u16 ss_if_crossRing;
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};
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struct [[gnu::aligned(16)]] FPUState
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{
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u8 buffer[512];
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};
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inline constexpr u32 page_base_of(u32 address)
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{
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return address & 0xfffff000;
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}
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class CPUID {
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public:
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CPUID(u32 function) { asm volatile("cpuid"
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: "=a"(m_eax), "=b"(m_ebx), "=c"(m_ecx), "=d"(m_edx)
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: "a"(function), "c"(0)); }
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u32 eax() const { return m_eax; }
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u32 ebx() const { return m_ebx; }
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u32 ecx() const { return m_ecx; }
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u32 edx() const { return m_edx; }
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private:
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u32 m_eax { 0xffffffff };
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u32 m_ebx { 0xffffffff };
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u32 m_ecx { 0xffffffff };
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u32 m_edx { 0xffffffff };
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};
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inline void read_tsc(u32& lsw, u32& msw)
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{
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asm volatile("rdtsc"
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: "=d"(msw), "=a"(lsw));
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}
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struct Stopwatch {
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union SplitQword {
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struct {
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uint32_t lsw;
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uint32_t msw;
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};
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uint64_t qw { 0 };
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};
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public:
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Stopwatch(const char* name)
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: m_name(name)
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{
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read_tsc(m_start.lsw, m_start.msw);
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}
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~Stopwatch()
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{
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SplitQword end;
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read_tsc(end.lsw, end.msw);
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uint64_t diff = end.qw - m_start.qw;
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dbgprintf("Stopwatch(%s): %Q ticks\n", m_name, diff);
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}
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private:
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const char* m_name { nullptr };
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SplitQword m_start;
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};
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class MSR {
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uint32_t m_msr;
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public:
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static bool have()
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{
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CPUID id(1);
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return (id.edx() & (1 << 5)) != 0;
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}
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MSR(const MSR&) = delete;
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MSR& operator=(const MSR&) = delete;
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MSR(uint32_t msr):
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m_msr(msr)
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{
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}
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void get(u32& low, u32& high)
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{
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asm volatile("rdmsr"
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: "=a"(low), "=d"(high)
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: "c"(m_msr));
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}
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void set(u32 low, u32 high)
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{
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asm volatile("wrmsr"
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:: "a"(low), "d"(high), "c"(m_msr));
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}
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};
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