Commit graph

4137 commits

Author SHA1 Message Date
Andreas Kling 497c4c3858 Kernel: Let's also not reverse the blocking flag for FIONBIO.. 2021-03-29 08:59:22 +02:00
Andreas Kling 0f270afda8 Kernel: Let's allow unsetting non-blocking mode with FIONBIO as well
Thanks to almightyhydra for pointing this out! :^)
2021-03-29 08:58:13 +02:00
Idan Horowitz 9f656b6fa9 LibCoreDump+CrashDaemon: Compress coredumps
Most coredumps contain large amounts of consecutive null bytes and as
such are a prime candidate for compression.

This commit makes CrashDaemon compress files once the kernel finishes
emitting them, as well as adds the functionality needed in LibCoreDump
to then parse them.
2021-03-28 20:42:33 +02:00
Andreas Kling 5f71bf0cc7 Kernel+LibC: Implement sys$ioctl() FIONBIO
This is another (older) way of making a file descriptor non-blocking.
2021-03-28 17:50:08 +02:00
Liav A 3547d90a0f Kernel/Storage: Select the drive before working with busmaster register
This is a "quirk" I've observed on a Intel ICH7 test machine. Apparently
we need to select the device (master or slave) before starting to work
with the bus master register.
It's very possible that other machines are requiring this step to happen
before the DMA transfer can occur correctly.

Also, when reading with DMA, we should set the transfer direction before
clearing the interrupt status.

For the sake of completeness, I added a few lines in places that I
deemed it to be reasonable to clear the interrupt status there.
2021-03-27 16:40:16 +01:00
Liav A 1d0c183388 Kernel/Storage: Add some debug printing about IDE controllers 2021-03-27 16:40:16 +01:00
Liav A 186e03b99d Kernel/Storage: Remove redundant public declaration in IDEController.h 2021-03-27 16:40:16 +01:00
Liav A b96e4c1308 Kernel/Storage: Use more locking in the IDE code
This change should make it less possible for race conditions to happen
and cause fatal errors when accessing the hardware.
2021-03-27 16:40:16 +01:00
Liav A 8b446fb579 Kernel/Storage: Add support for non-bus mastering IDE controllers
Although unlikely to happen, a user can have an IDE controller that
doesn't support bus master capability. If that's the case, we need to
check for this, and create an IDEChannel (not BMIDEChannel) to allow
IO operations with the controller.
2021-03-27 16:40:16 +01:00
Liav A 833a6bd047 Kernel/Storage: Move IDE bus master handling code into a separate class
If the user requests to force PIO mode, we just create IDEChannel
objects which are capable of sending PIO commands only.
However, if the user doesn't force PIO mode, we create BMIDEChannel
objects, which are sending DMA commands.

This change is somewhat simplifying the code, so each class is
supporting its type of operation - PIO or DMA. The PATADiskDevice
should not care if DMA is enabled or not.

Later on, we could write an IDEChannel class for UDMA modes,
that are available and documented on Intel specifications for their IDE
controllers.
2021-03-27 16:40:16 +01:00
Liav A dfb6b296cf Kernel: Make IDEChannel Ref-counted
Technically not supported by the original ATA specification, IDE
hot swapping is still in practice possible, so the only sane way
to start support it is with ref-counting the IDEChannel object so if we
remove a PATADiskDevice, it's not gone with it.
2021-03-27 16:40:16 +01:00
Liav A 531037db7e Kernel: Remove support for CHS addressing
An article about IDE limits states that:
"Hard drives over 8.4 GB are supposed to report their geometry as
16383/16/63. This in effect means that the `geometry' is obsolete, and
the total disk size can no longer be computed from the geometry, but is
found in the LBA capacity field returned by the IDENTIFY command.
Hard drives over 137.4 GB are supposed to report an LBA capacity of
0xfffffff = 268435455 sectors (137438952960 bytes). Now the actual disk
size is found in the new 48-capacity field."
(https://tldp.org/HOWTO/Large-Disk-HOWTO-4.html) which is the main
reason to not support CHS as harddrives with less than 8.4 GB capacity
are completely obsolete.

Another good reason is that virtually any harddrive in the last 20 years
or so, supports LBA mode. Therefore, it's probably OK to just ignore CHS
as it's unlikely to encounter a harddrive that doesn't support LBA.

This is somewhat simplifying the IDE initialization and access code.
Also, we should use the ATAIdentifyBlock structure if possible,
so now we do it instead of using macros to calculate offsets.

With the usage of the ATAIdentifyBlock structure, we now use the
48-bit LBA max count if the drive indicates it supports 48-bit LBA mode.
2021-03-27 16:40:16 +01:00
Liav A 4bb8986752 Kernel: Generalize the ATAIdentifyBlock structure 2021-03-27 16:40:16 +01:00
Michel Hermier ff0d4c6f7c Kernel: Remove unused WorkQueue::m_name. 2021-03-26 16:54:05 +01:00
Michel Hermier 51ad3da999 Kernel: Remove unused MBRPartitionTable::m_partitions_count. 2021-03-26 16:54:05 +01:00
Michel Hermier 4ac49eabd5 Kernel: Remove unused FileBlockCondition::m_file. 2021-03-26 16:54:05 +01:00
Michel Hermier a359f477a7 Kernel: Remove unused EBRPartitionTable::m_partitions_count. 2021-03-26 16:54:05 +01:00
Michel Hermier 37be679d6e Kernel: Remove unused AHCIPort::ScatterList::m_device_block_size. 2021-03-26 16:54:05 +01:00
Liav A 663dea4a60 Kernel: Return real handler purpose when registered to spurious handler
If we registered a real interrupt handler to a spurious one, we should
return its purpose instead of the spurious purpose string.
2021-03-23 19:27:00 +01:00
Liav A fe761e7412 Kernel: Handle real IRQs from line 7 when using the PIC
If we have a real IRQ7 to handle, let's make sure the handler knows to
check if it really occured for this value and not only for IRQ15.
2021-03-23 19:27:00 +01:00
Liav A b25f84daaa Revert "Kernel/AHCI: Add a boot argument to force AHCI to operate on IRQ 11"
This reverts commit cfc2f33dcb.

We can't actually change the IRQ line value and expect the device
to work with it (this was my mistake).
That register is R/W so the firmware can figure out IRQ routing and put
the correct value and write it to the Interrupt line register.
2021-03-23 19:27:00 +01:00
Liav A 6440beeffe Kernel/AHCI: Shift the call to reset() for the WorkQueue 2021-03-21 13:41:09 +01:00
Liav A 2ae9de77bb Kernel/AHCI: Reorder complete_current_request
Clear the m_current_request before signalling the end of request.
2021-03-21 13:41:09 +01:00
Liav A cfc2f33dcb Kernel/AHCI: Add a boot argument to force AHCI to operate on IRQ 11
As a compromise, if the fimrware decided to set the IRQ line to be 7,
or something else we can't deal with, the user can simply force the code
to work with IRQ 11, with the boot argument "force_ahci_irq_11" being
set to "on".
2021-03-21 13:41:09 +01:00
Liav A 36a82188a8 Kernel/PCI: Allow to set the PCI IRQ line of a device
This will be used later by the AHCI code to set the IRQ line to be 11,
if hardware by mistake changed the value to be something we can't deal
with.
2021-03-21 13:41:09 +01:00
Liav A 6c03fdc1ef Kernel/AHCI: Don't set the PRDBC when accessing the device
This resulted in fatal error when trying to write to real hard drive
I tested, so we only set the counts in the scatter/gather list later.
2021-03-21 13:41:09 +01:00
Liav A 0b1fa97b30 Kernel/AHCI: Use interrupts for IO operations
Instead of polling if the device ended the operation, we can just use
interrupts for signalling about end of IO operation.
In similar way, we use interrupts during device detection.

Also, we use the new Work Queue mechanism introduced by @tomuta to allow
better performance and stability :)
2021-03-21 13:41:09 +01:00
Liav A 21bb7fd5c9 Kernel/AHCI: Add a method to get raw interrupt enable register 2021-03-21 13:41:09 +01:00
Tom 20cccda731 Kernel: Add simplistic work queues
We can't use deferred functions for anything that may require preemption,
such as copying from/to user or accessing the disk. For those purposes
we should use a work queue, which is essentially a kernel thread that
may be preempted or blocked.
2021-03-21 13:41:09 +01:00
Liav A 314f04b896 Kernel: Fix undefined behavior due to shifting out of bounds 2021-03-21 13:41:09 +01:00
Hendiadyoin1 611b3c2c49 Kernel: Make TSS use in thread generic
This way it won't be architecture dependent
2021-03-21 09:35:23 +01:00
Hendiadyoin1 ce4f43a192 Kernel::x86_64: Re-copy boot.S and add longmode in
Now we should have the posibility to run in longmode, after enabling it
in the gdt
2021-03-21 09:35:23 +01:00
Hendiadyoin1 61240aaad3 Kernel: Make IDT Entries their one struct
This is to make them a bit more transparent, and with a bit of Compiler
magic we get the 64-bit implementation in the same package
2021-03-21 09:35:23 +01:00
Hendiadyoin1 0d934fc991 Kernel::CPU: Move headers into common directory
Alot of code is shared between i386/i686/x86 and x86_64
and a lot probably will be used for compatability modes.
So we start by moving the headers into one Directory.
We will probalby be able to move some cpp files aswell.
2021-03-21 09:35:23 +01:00
Hendiadyoin1 5a8cc07485 Kernel: Add TSS64 and Desciptor for 64-bit 2021-03-21 09:35:23 +01:00
Hendiadyoin1 0b04363b01 Kernel: Renable UHCIController on 64-bit processors 2021-03-21 09:35:23 +01:00
Itamar 2365e06b12 Kernel: Set TLS-related members of Process after loading static program
We previously ignored these values in the return value of
load_elf_object, which causes us to not allocate a TLS region for
statically-linked programs.
2021-03-19 22:55:53 +01:00
Andreas Kling d48666489c Kernel: Make FileDescription::seek() return KResultOr<off_t>
This exposed a bunch of places where errors were not propagated,
so this patch is forced to deal with them as well.
2021-03-19 10:44:25 +01:00
Jean-Baptiste Boric eea5a5ed5d Kernel: Make block-based file system code 64 bit ready 2021-03-19 09:15:19 +01:00
Jean-Baptiste Boric 6698fd84ff Kernel: Refactor storage stack with u64 as mmap offset 2021-03-19 09:15:19 +01:00
Luke 3507397fed Kernel/Storage: Recover from fatal AHCI error on TFES, HBDS and HBFS
These errors are classed as fatal, so we need to recover from them.
Found while trying to debug AHCI boot on VMware Player,
where I got TFES.

From the spec: "Fatal errors (signified by the setting of PxIS.HBFS,
PxIS.HBDS, PxIS.IFS, or PxIS.TFES) will cause the HBA to enter
the ERR:Fatal state"

We were already recovering from IFS.
2021-03-18 07:52:15 +01:00
Luke cf9ce0d857 Kernel/Storage: Add a whole bunch of AHCI debug output 2021-03-18 07:52:15 +01:00
Luke b7dd5dc7c3 Kernel/Storage: Add AHCI Extended HBA Capabilities 2021-03-18 07:52:15 +01:00
Luke 64a240f4df Kernel/Storage: Fix typos in HBA capabilities 2021-03-18 07:52:15 +01:00
Jean-Baptiste Boric 71b433a6f9 Kernel: Add 64 bit file size support to Ext2FS 2021-03-17 23:22:42 +01:00
Jean-Baptiste Boric 7a079f7780 LibC+Kernel: Switch off_t to 64 bits 2021-03-17 23:22:42 +01:00
Jean-Baptiste Boric b05b4d4b24 Kernel: Refactor storage stack with u64 as file operations offset 2021-03-17 23:22:42 +01:00
Jean-Baptiste Boric 999c57ef2d Kernel: Refactor storage stack with u64 as block index 2021-03-17 23:22:42 +01:00
Jean-Baptiste Boric 9a3aa7eb0b Kernel: Refactor storage stack with u64 as number of blocks 2021-03-17 23:22:42 +01:00
Jean-Baptiste Boric aeef14ae28 Kernel: Rationalize logs inside Ext2Fs 2021-03-17 23:22:42 +01:00