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https://github.com/SerenityOS/serenity
synced 2024-07-21 18:15:58 +00:00
Kernel: Restore ATA PIO functionality
First, before this change, specifying 'force_pio' in the kernel commandline was meaningless because we nevertheless set the DMA flag to be enabled. Also, we had a problem in which we used IO::repeated_out16() in PIO write method. This might work on buggy emulators, but I suspect that on real hardware this code will fail. The most difficult problem was to restore the PIO read operation. Apparently, it seems that we can't use IO::repeated_in16() here because it will read zeroed data. Currently we rely on a simple loop that invokes IO::in16() to a buffer. Also, the interrupt handling stage in the PIO read method is moved to be handled inside the loop of reading the requested sectors.
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3f698db85d
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@ -136,10 +136,9 @@ PATAChannel::PATAChannel(PCI::Address address, ChannelType type, bool force_pio)
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{
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disable_irq();
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m_dma_enabled.resource() = true;
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m_dma_enabled.resource() = !force_pio;
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ProcFS::add_sys_bool("ide_dma", m_dma_enabled);
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m_prdt_page = MM.allocate_supervisor_physical_page();
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initialize(force_pio);
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detect_disks();
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disable_irq();
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@ -157,14 +156,15 @@ void PATAChannel::prepare_for_irq()
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void PATAChannel::initialize(bool force_pio)
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{
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PCI::enable_interrupt_line(pci_address());
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if (force_pio) {
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klog() << "PATAChannel: Requested to force PIO mode; not setting up DMA";
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return;
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}
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// Let's try to set up DMA transfers.
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PCI::enable_bus_mastering(pci_address());
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PCI::enable_interrupt_line(pci_address());
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m_prdt_page = MM.allocate_supervisor_physical_page();
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prdt().end_of_table = 0x8000;
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m_dma_buffer_page = MM.allocate_supervisor_physical_page();
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klog() << "PATAChannel: Bus master IDE: " << m_bus_master_base;
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@ -402,57 +402,66 @@ bool PATAChannel::ata_write_sectors_with_dma(u32 lba, u16 count, const u8* inbuf
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return true;
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}
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bool PATAChannel::ata_read_sectors(u32 start_sector, u16 count, u8* outbuf, bool slave_request)
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bool PATAChannel::ata_read_sectors(u32 lba, u16 count, u8* outbuf, bool slave_request)
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{
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ASSERT(count <= 256);
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LOCKER(s_lock());
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#ifdef PATA_DEBUG
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dbg() << "PATAChannel::ata_read_sectors request (" << count << " sector(s) @ " << start_sector << " into " << outbuf << ")";
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dbg() << "PATAChannel::ata_read_sectors request (" << count << " sector(s) @ " << lba << " into " << outbuf << ")";
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#endif
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while (m_io_base.offset(ATA_REG_STATUS).in<u8>() & ATA_SR_BSY)
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;
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#ifdef PATA_DEBUG
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klog() << "PATAChannel: Reading " << count << " sector(s) @ LBA " << start_sector;
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klog() << "PATAChannel: Reading " << count << " sector(s) @ LBA " << lba;
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#endif
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u8 devsel = 0xe0;
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if (slave_request)
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devsel |= 0x10;
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m_io_base.offset(ATA_REG_SECCOUNT0).out<u8>(count == 256 ? 0 : LSB(count));
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m_io_base.offset(ATA_REG_LBA0).out<u8>(start_sector & 0xff);
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m_io_base.offset(ATA_REG_LBA1).out<u8>((start_sector >> 8) & 0xff);
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m_io_base.offset(ATA_REG_LBA2).out<u8>((start_sector >> 16) & 0xff);
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m_io_base.offset(ATA_REG_HDDEVSEL).out<u8>(devsel | ((start_sector >> 24) & 0xf));
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m_control_base.offset(ATA_CTL_CONTROL).out<u8>(0);
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m_io_base.offset(ATA_REG_HDDEVSEL).out<u8>(devsel | (static_cast<u8>(slave_request) << 4) | 0x40);
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io_delay();
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IO::out8(0x3F6, 0x08);
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while (!(m_io_base.offset(ATA_REG_STATUS).in<u8>() & ATA_SR_DRDY))
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;
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m_io_base.offset(ATA_REG_FEATURES).out<u8>(0);
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prepare_for_irq();
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m_io_base.offset(ATA_REG_COMMAND).out<u8>(ATA_CMD_READ_PIO);
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wait_for_irq();
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m_io_base.offset(ATA_REG_SECCOUNT0).out<u8>(0);
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m_io_base.offset(ATA_REG_LBA0).out<u8>(0);
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m_io_base.offset(ATA_REG_LBA1).out<u8>(0);
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m_io_base.offset(ATA_REG_LBA2).out<u8>(0);
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if (m_device_error)
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return false;
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m_io_base.offset(ATA_REG_SECCOUNT0).out<u8>(count);
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m_io_base.offset(ATA_REG_LBA0).out<u8>((lba & 0x000000ff) >> 0);
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m_io_base.offset(ATA_REG_LBA1).out<u8>((lba & 0x0000ff00) >> 8);
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m_io_base.offset(ATA_REG_LBA2).out<u8>((lba & 0x00ff0000) >> 16);
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for (int i = 0; i < count; i++) {
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io_delay();
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while (m_io_base.offset(ATA_REG_STATUS).in<u8>() & ATA_SR_BSY)
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;
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u8 status = m_io_base.offset(ATA_REG_STATUS).in<u8>();
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ASSERT(status & ATA_SR_DRQ);
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#ifdef PATA_DEBUG
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dbg() << "PATAChannel: Retrieving 512 bytes (part " << i << ") (status=" << String::format("%b", status) << "), outbuf=(" << (outbuf + (512 * i)) << ")...";
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#endif
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IO::repeated_in16(m_io_base.offset(ATA_REG_DATA).get(), outbuf + (512 * i), 256);
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for (;;) {
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auto status = m_io_base.offset(ATA_REG_STATUS).in<u8>();
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if (!(status & ATA_SR_BSY) && (status & ATA_SR_DRDY))
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break;
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}
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m_io_base.offset(ATA_REG_COMMAND).out<u8>(ATA_CMD_READ_PIO);
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for (int i = 0; i < count; i++) {
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prepare_for_irq();
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wait_for_irq();
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if (m_device_error)
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return false;
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u8 status = m_control_base.offset(ATA_CTL_ALTSTATUS).in<u8>();
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ASSERT(!(status & ATA_SR_BSY));
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auto* buffer = (u16*)(outbuf + i * 512);
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#ifdef PATA_DEBUG
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dbg() << "PATAChannel: Retrieving 512 bytes (part " << i << ") (status=" << String::format("%b", status) << "), outbuf=(" << buffer << ")...";
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#endif
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for (int i = 0; i < 256; i++) {
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buffer[i] = IO::in16(m_io_base.offset(ATA_REG_DATA).get());
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}
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}
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return true;
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}
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@ -489,7 +498,7 @@ bool PATAChannel::ata_write_sectors(u32 start_sector, u16 count, const u8* inbuf
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for (int i = 0; i < count; i++) {
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io_delay();
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while (m_io_base.offset(ATA_REG_STATUS).in<u8>() & ATA_SR_BSY)
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while ((m_io_base.offset(ATA_REG_STATUS).in<u8>() & ATA_SR_BSY) || !(m_io_base.offset(ATA_REG_STATUS).in<u8>() & ATA_SR_DRQ))
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;
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u8 status = m_io_base.offset(ATA_REG_STATUS).in<u8>();
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@ -499,7 +508,10 @@ bool PATAChannel::ata_write_sectors(u32 start_sector, u16 count, const u8* inbuf
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dbg() << "PATAChannel: Writing 512 bytes (part " << i << ") (status=" << String::format("%b", status) << "), inbuf=(" << (inbuf + (512 * i)) << ")...";
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#endif
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IO::repeated_out16(m_io_base.offset(ATA_REG_DATA).get(), inbuf + (512 * i), 256);
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auto* buffer = (u16*)(const_cast<u8*>(inbuf) + i * 512);
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for (int i = 0; i < 256; i++) {
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IO::out16(m_io_base.offset(ATA_REG_DATA).get(), buffer[i]);
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}
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prepare_for_irq();
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wait_for_irq();
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status = m_io_base.offset(ATA_REG_STATUS).in<u8>();
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