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UserspaceEmulator: Tweak INC and SAR helpers to not be SoftCPU members
It's quite nice having these as compartmentalized free functions.
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parent
e852768ba6
commit
7d41b95071
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@ -439,7 +439,7 @@ void SoftCPU::IMUL_reg32_RM32_imm32(const X86::Instruction&) { TODO(); }
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void SoftCPU::IMUL_reg32_RM32_imm8(const X86::Instruction&) { TODO(); }
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template<typename T>
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T SoftCPU::inc_impl(T data)
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static T op_inc(SoftCPU& cpu, T data)
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{
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T result = 0;
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u32 new_flags = 0;
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@ -463,33 +463,33 @@ T SoftCPU::inc_impl(T data)
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"pop %%ebx"
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: "=b"(new_flags));
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set_flags_oszap(new_flags);
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cpu.set_flags_oszap(new_flags);
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return result;
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}
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void SoftCPU::INC_RM16(const X86::Instruction& insn)
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{
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insn.modrm().write16(*this, insn, inc_impl(insn.modrm().read16(*this, insn)));
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insn.modrm().write16(*this, insn, op_inc(*this, insn.modrm().read16(*this, insn)));
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}
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void SoftCPU::INC_RM32(const X86::Instruction& insn)
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{
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insn.modrm().write32(*this, insn, inc_impl(insn.modrm().read32(*this, insn)));
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insn.modrm().write32(*this, insn, op_inc(*this, insn.modrm().read32(*this, insn)));
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}
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void SoftCPU::INC_RM8(const X86::Instruction& insn)
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{
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insn.modrm().write8(*this, insn, inc_impl(insn.modrm().read8(*this, insn)));
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insn.modrm().write8(*this, insn, op_inc(*this, insn.modrm().read8(*this, insn)));
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}
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void SoftCPU::INC_reg16(const X86::Instruction& insn)
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{
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gpr16(insn.reg16()) = inc_impl(gpr16(insn.reg16()));
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gpr16(insn.reg16()) = op_inc(*this, gpr16(insn.reg16()));
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}
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void SoftCPU::INC_reg32(const X86::Instruction& insn)
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{
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gpr32(insn.reg32()) = inc_impl(gpr32(insn.reg32()));
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gpr32(insn.reg32()) = op_inc(*this, gpr32(insn.reg32()));
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}
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void SoftCPU::INSB(const X86::Instruction&) { TODO(); }
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@ -762,7 +762,7 @@ void SoftCPU::SAHF(const X86::Instruction&) { TODO(); }
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void SoftCPU::SALC(const X86::Instruction&) { TODO(); }
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template<typename T>
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T SoftCPU::sar_impl(T data, u8 steps)
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static T op_sar(SoftCPU& cpu, T data, u8 steps)
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{
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if (steps == 0)
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return data;
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@ -785,62 +785,62 @@ T SoftCPU::sar_impl(T data, u8 steps)
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"pop %%eax"
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: "=a"(new_flags));
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set_flags_oszapc(new_flags);
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cpu.set_flags_oszapc(new_flags);
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return result;
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}
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void SoftCPU::SAR_RM16_1(const X86::Instruction& insn)
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{
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auto data = insn.modrm().read16(*this, insn);
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insn.modrm().write16(*this, insn, sar_impl(data, 1));
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insn.modrm().write16(*this, insn, op_sar(*this, data, 1));
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}
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void SoftCPU::SAR_RM16_CL(const X86::Instruction& insn)
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{
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auto data = insn.modrm().read16(*this, insn);
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insn.modrm().write16(*this, insn, sar_impl(data, cl()));
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insn.modrm().write16(*this, insn, op_sar(*this, data, cl()));
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}
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void SoftCPU::SAR_RM16_imm8(const X86::Instruction& insn)
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{
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auto data = insn.modrm().read16(*this, insn);
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insn.modrm().write16(*this, insn, sar_impl(data, insn.imm8()));
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insn.modrm().write16(*this, insn, op_sar(*this, data, insn.imm8()));
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}
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void SoftCPU::SAR_RM32_1(const X86::Instruction& insn)
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{
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auto data = insn.modrm().read32(*this, insn);
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insn.modrm().write32(*this, insn, sar_impl(data, 1));
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insn.modrm().write32(*this, insn, op_sar(*this, data, 1));
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}
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void SoftCPU::SAR_RM32_CL(const X86::Instruction& insn)
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{
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auto data = insn.modrm().read32(*this, insn);
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insn.modrm().write32(*this, insn, sar_impl(data, cl()));
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insn.modrm().write32(*this, insn, op_sar(*this, data, cl()));
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}
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void SoftCPU::SAR_RM32_imm8(const X86::Instruction& insn)
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{
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auto data = insn.modrm().read32(*this, insn);
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insn.modrm().write32(*this, insn, sar_impl(data, insn.imm8()));
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insn.modrm().write32(*this, insn, op_sar(*this, data, insn.imm8()));
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}
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void SoftCPU::SAR_RM8_1(const X86::Instruction& insn)
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{
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auto data = insn.modrm().read8(*this, insn);
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insn.modrm().write8(*this, insn, sar_impl(data, 1));
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insn.modrm().write8(*this, insn, op_sar(*this, data, 1));
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}
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void SoftCPU::SAR_RM8_CL(const X86::Instruction& insn)
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{
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auto data = insn.modrm().read8(*this, insn);
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insn.modrm().write8(*this, insn, sar_impl(data, cl()));
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insn.modrm().write8(*this, insn, op_sar(*this, data, cl()));
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}
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void SoftCPU::SAR_RM8_imm8(const X86::Instruction& insn)
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{
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auto data = insn.modrm().read8(*this, insn);
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insn.modrm().write8(*this, insn, sar_impl(data, insn.imm8()));
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insn.modrm().write8(*this, insn, op_sar(*this, data, insn.imm8()));
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}
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void SoftCPU::SBB_AL_imm8(const X86::Instruction&) { TODO(); }
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@ -767,11 +767,6 @@ private:
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template<bool update_dest, typename Op>
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void generic_reg8_RM8(Op, const X86::Instruction&);
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template<typename T>
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T sar_impl(T data, u8 steps);
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template<typename T>
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T inc_impl(T);
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private:
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Emulator& m_emulator;
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