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https://github.com/SerenityOS/serenity
synced 2024-07-24 11:35:13 +00:00
Kernel/USB: Add support for async & interrupt transfers
Add support for async transfers by using a separate kernel task to poll a list of active async transfers on a set time interval, and invoke their user-provided callback function when they are complete. Also add support for the interrupt class of transfers, building off of this async functionality.
This commit is contained in:
b14ckcat
Andrew Kaster
parent
1aa16b4dd4
commit
7400eb3640
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@ -5,6 +5,7 @@
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#include <AK/Find.h>
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#include <AK/Platform.h>
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#include <Kernel/Arch/Delay.h>
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#include <Kernel/Bus/PCI/API.h>
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@ -78,6 +79,7 @@ ErrorOr<void> UHCIController::initialize()
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dmesgln("UHCI: I/O base {}", m_registers_io_window);
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dmesgln("UHCI: Interrupt line: {}", interrupt_number());
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TRY(spawn_async_poll_process());
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TRY(spawn_port_process());
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TRY(reset());
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@ -88,6 +90,7 @@ UNMAP_AFTER_INIT UHCIController::UHCIController(PCI::DeviceIdentifier const& pci
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: PCI::Device(pci_device_identifier.address())
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, IRQHandler(pci_device_identifier.interrupt_line().value())
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, m_registers_io_window(move(registers_io_window))
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, m_async_lock(LockRank::None)
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, m_schedule_lock(LockRank::None)
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{
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}
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@ -132,14 +135,11 @@ UNMAP_AFTER_INIT ErrorOr<void> UHCIController::create_structures()
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{
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m_queue_head_pool = TRY(UHCIDescriptorPool<QueueHead>::try_create("Queue Head Pool"sv));
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// Used as a sentinel value to loop back to the beginning of the list
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// Doesn't do anything other than give interrupt transfer queues something to set as prev QH so that we don't have to handle that as an extra edge case
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m_schedule_begin_anchor = allocate_queue_head();
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// Each interrupt QH anchor in the array is linked into the schedule so that
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// it is executed once every (2^i) milliseconds, where i is it's index
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for (int i = 0; i < NUMBER_OF_INTERRUPT_QHS; i++) {
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m_interrupt_qh_anchor_arr[i] = allocate_queue_head();
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}
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// Create the Full Speed, Low Speed Control and Bulk Queue Heads
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// Create the Interrupt, Full Speed, Low Speed Control and Bulk Queue Heads
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m_interrupt_qh_anchor = allocate_queue_head();
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m_ls_control_qh_anchor = allocate_queue_head();
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m_fs_control_qh_anchor = allocate_queue_head();
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m_bulk_qh_anchor = allocate_queue_head();
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@ -201,15 +201,11 @@ UNMAP_AFTER_INIT void UHCIController::setup_schedule()
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// Not specified in the datasheet, however, is another Queue Head with an "inactive" Transfer Descriptor. This
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// is to circumvent a bug in the silicon of the PIIX4's UHCI controller.
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// https://github.com/openbsd/src/blob/master/sys/dev/usb/uhci.c#L390
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m_schedule_begin_anchor->link_next_queue_head(m_interrupt_qh_anchor_arr[0]);
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m_schedule_begin_anchor->link_next_queue_head(m_interrupt_qh_anchor);
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m_schedule_begin_anchor->terminate_element_link_ptr();
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for (int i = 0; i < NUMBER_OF_INTERRUPT_QHS - 1; i++) {
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m_interrupt_qh_anchor_arr[i]->link_next_queue_head(m_interrupt_qh_anchor_arr[i + 1]);
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m_interrupt_qh_anchor_arr[i]->terminate_element_link_ptr();
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}
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m_interrupt_qh_anchor_arr[NUMBER_OF_INTERRUPT_QHS - 1]->link_next_queue_head(m_ls_control_qh_anchor);
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m_interrupt_qh_anchor_arr[NUMBER_OF_INTERRUPT_QHS - 1]->terminate_element_link_ptr();
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m_interrupt_qh_anchor->link_next_queue_head(m_ls_control_qh_anchor);
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m_interrupt_qh_anchor->terminate_element_link_ptr();
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m_ls_control_qh_anchor->link_next_queue_head(m_fs_control_qh_anchor);
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m_ls_control_qh_anchor->terminate_element_link_ptr();
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@ -227,20 +223,12 @@ UNMAP_AFTER_INIT void UHCIController::setup_schedule()
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u32* framelist = reinterpret_cast<u32*>(m_framelist->vaddr().as_ptr());
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for (int frame_num = 0; frame_num < UHCI_NUMBER_OF_FRAMES; frame_num++) {
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auto frame_iso_td = m_iso_td_list.at(frame_num % UHCI_NUMBER_OF_ISOCHRONOUS_TDS);
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// Each frame pointer points to iso_td % NUM_ISO_TDS
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for (int i = NUMBER_OF_INTERRUPT_QHS - 1; i >= 0; i--) {
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if (frame_num % (1 << i) == 0) {
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frame_iso_td->link_queue_head(m_interrupt_qh_anchor_arr[i]->paddr());
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break;
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}
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}
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auto& frame_iso_td = m_iso_td_list.at(frame_num % UHCI_NUMBER_OF_ISOCHRONOUS_TDS);
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frame_iso_td->link_queue_head(m_schedule_begin_anchor->paddr());
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framelist[frame_num] = frame_iso_td->paddr();
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}
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for (int i = 0; i < NUMBER_OF_INTERRUPT_QHS; i++) {
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m_interrupt_qh_anchor_arr[i]->print();
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}
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m_interrupt_qh_anchor->print();
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m_ls_control_qh_anchor->print();
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m_fs_control_qh_anchor->print();
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m_bulk_qh_anchor->print();
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@ -387,6 +375,70 @@ void UHCIController::dequeue_qh(QueueHead* transfer_queue)
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transfer_queue->prev_qh()->link_next_queue_head(transfer_queue->next_qh());
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}
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ErrorOr<QueueHead*> UHCIController::create_transfer_queue(Transfer& transfer)
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{
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Pipe& pipe = transfer.pipe();
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// Create a new descriptor chain
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TransferDescriptor* last_data_descriptor;
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TransferDescriptor* data_descriptor_chain;
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auto buffer_address = Ptr32<u8>(transfer.buffer_physical().as_ptr());
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TRY(create_chain(pipe, transfer.pipe().direction() == Pipe::Direction::In ? PacketID::IN : PacketID::OUT, buffer_address, pipe.max_packet_size(), transfer.transfer_data_size(), &data_descriptor_chain, &last_data_descriptor));
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last_data_descriptor->terminate();
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if constexpr (UHCI_VERBOSE_DEBUG) {
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if (data_descriptor_chain) {
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dbgln("Data TD");
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data_descriptor_chain->print();
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}
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}
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QueueHead* transfer_queue = allocate_queue_head();
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if (!transfer_queue) {
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free_descriptor_chain(data_descriptor_chain);
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return ENOMEM;
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}
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transfer_queue->attach_transfer_descriptor_chain(data_descriptor_chain);
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transfer_queue->set_transfer(&transfer);
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return transfer_queue;
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}
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ErrorOr<void> UHCIController::submit_async_transfer(NonnullOwnPtr<AsyncTransferHandle> async_handle, QueueHead* anchor, QueueHead* transfer_queue)
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{
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{
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SpinlockLocker locker { m_async_lock };
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auto iter = find_if(m_active_async_transfers.begin(), m_active_async_transfers.end(), [](auto& handle) { return handle == nullptr; });
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if (iter == m_active_async_transfers.end())
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return ENOMEM;
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*iter = move(async_handle);
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}
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enqueue_qh(transfer_queue, anchor);
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return {};
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}
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void UHCIController::cancel_async_transfer(NonnullLockRefPtr<Transfer> transfer)
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{
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SpinlockLocker locker { m_async_lock };
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auto iter = find_if(m_active_async_transfers.begin(), m_active_async_transfers.end(), [transfer](auto& handle) { return handle != nullptr && handle->transfer.ptr() == transfer.ptr(); });
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if (iter == m_active_async_transfers.end()) {
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dbgln("Error: couldn't cancel supplied async transfer");
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return; // We can't really do anything here, so just give up
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}
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auto& transfer_queue = (*iter)->qh;
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dequeue_qh(transfer_queue);
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free_descriptor_chain(transfer_queue->get_first_td());
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transfer_queue->free();
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m_queue_head_pool->release_to_pool(transfer_queue);
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*iter = nullptr;
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}
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ErrorOr<size_t> UHCIController::submit_control_transfer(Transfer& transfer)
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{
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Pipe& pipe = transfer.pipe(); // Short circuit the pipe related to this transfer
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@ -467,35 +519,11 @@ ErrorOr<size_t> UHCIController::submit_control_transfer(Transfer& transfer)
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ErrorOr<size_t> UHCIController::submit_bulk_transfer(Transfer& transfer)
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{
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Pipe& pipe = transfer.pipe();
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dbgln_if(UHCI_DEBUG, "UHCI: Received bulk transfer for address {}. Root Hub is at address {}.", pipe.device_address(), m_root_hub->device_address());
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// Create a new descriptor chain
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TransferDescriptor* last_data_descriptor;
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TransferDescriptor* data_descriptor_chain;
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auto buffer_address = Ptr32<u8>(transfer.buffer_physical().as_ptr());
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TRY(create_chain(pipe, transfer.pipe().direction() == Pipe::Direction::In ? PacketID::IN : PacketID::OUT, buffer_address, pipe.max_packet_size(), transfer.transfer_data_size(), &data_descriptor_chain, &last_data_descriptor));
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last_data_descriptor->terminate();
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if constexpr (UHCI_VERBOSE_DEBUG) {
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if (data_descriptor_chain) {
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dbgln("Data TD");
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data_descriptor_chain->print();
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}
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}
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QueueHead* transfer_queue = allocate_queue_head();
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if (!transfer_queue) {
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free_descriptor_chain(data_descriptor_chain);
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return ENOMEM;
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}
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transfer_queue->attach_transfer_descriptor_chain(data_descriptor_chain);
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transfer_queue->set_transfer(&transfer);
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auto transfer_queue = TRY(create_transfer_queue(transfer));
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enqueue_qh(transfer_queue, m_bulk_qh_anchor);
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dbgln_if(UHCI_DEBUG, "UHCI: Received bulk transfer for address {}. Root Hub is at address {}.", transfer.pipe().device_address(), m_root_hub->device_address());
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size_t transfer_size = 0;
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while (!transfer.complete()) {
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transfer_size = poll_transfer_queue(*transfer_queue);
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@ -510,6 +538,21 @@ ErrorOr<size_t> UHCIController::submit_bulk_transfer(Transfer& transfer)
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return transfer_size;
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}
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ErrorOr<void> UHCIController::submit_async_interrupt_transfer(NonnullLockRefPtr<Transfer> transfer, u16 ms_interval)
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{
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dbgln_if(UHCI_DEBUG, "UHCI: Received interrupt transfer for address {}. Root Hub is at address {}.", transfer->pipe().device_address(), m_root_hub->device_address());
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if (ms_interval == 0) {
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return EINVAL;
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}
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auto transfer_queue = TRY(create_transfer_queue(*transfer));
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auto async_transfer_handle = TRY(adopt_nonnull_own_or_enomem(new (nothrow) AsyncTransferHandle { transfer, transfer_queue, ms_interval }));
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TRY(submit_async_transfer(move(async_transfer_handle), m_interrupt_qh_anchor, transfer_queue));
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return {};
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}
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size_t UHCIController::poll_transfer_queue(QueueHead& transfer_queue)
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{
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Transfer* transfer = transfer_queue.transfer();
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@ -556,6 +599,33 @@ ErrorOr<void> UHCIController::spawn_port_process()
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return {};
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}
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ErrorOr<void> UHCIController::spawn_async_poll_process()
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{
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LockRefPtr<Thread> async_poll_thread;
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(void)Process::create_kernel_process(async_poll_thread, TRY(KString::try_create("UHCI Async Poll Task"sv)), [&] {
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u16 poll_interval_ms = 1024;
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for (;;) {
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{
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SpinlockLocker locker { m_async_lock };
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for (OwnPtr<AsyncTransferHandle>& handle : m_active_async_transfers) {
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if (handle != nullptr) {
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poll_interval_ms = min(poll_interval_ms, handle->ms_poll_interval);
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QueueHead* qh = handle->qh;
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for (auto td = qh->get_first_td(); td != nullptr && !td->active(); td = td->next_td()) {
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if (td->next_td() == nullptr) { // Finished QH
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handle->transfer->invoke_async_callback();
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qh->reinitialize(); // Set the QH to be active again
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}
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}
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}
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}
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}
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(void)Thread::current()->sleep(Time::from_milliseconds(poll_interval_ms));
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}
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});
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return {};
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}
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bool UHCIController::handle_irq(RegisterState const&)
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{
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u32 status = read_usbsts();
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@ -31,7 +31,6 @@ class UHCIController final
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static constexpr u8 MAXIMUM_NUMBER_OF_TDS = 128; // Upper pool limit. This consumes the second page we have allocated
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static constexpr u8 MAXIMUM_NUMBER_OF_QHS = 64;
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static constexpr u8 NUMBER_OF_INTERRUPT_QHS = 11;
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public:
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static constexpr u8 NUMBER_OF_ROOT_PORTS = 2;
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@ -44,10 +43,16 @@ public:
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virtual ErrorOr<void> reset() override;
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virtual ErrorOr<void> stop() override;
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virtual ErrorOr<void> start() override;
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ErrorOr<void> spawn_async_poll_process();
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ErrorOr<void> spawn_port_process();
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ErrorOr<QueueHead*> create_transfer_queue(Transfer& transfer);
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ErrorOr<void> submit_async_transfer(NonnullOwnPtr<AsyncTransferHandle> async_handle, QueueHead* anchor, QueueHead* transfer_queue);
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virtual void cancel_async_transfer(NonnullLockRefPtr<Transfer> transfer) override;
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virtual ErrorOr<size_t> submit_control_transfer(Transfer& transfer) override;
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virtual ErrorOr<size_t> submit_bulk_transfer(Transfer& transfer) override;
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virtual ErrorOr<void> submit_async_interrupt_transfer(NonnullLockRefPtr<Transfer> transfer, u16 ms_interval) override;
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void get_port_status(Badge<UHCIRootHub>, u8, HubStatus&);
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ErrorOr<void> set_port_feature(Badge<UHCIRootHub>, u8, HubFeatureSelector);
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@ -95,15 +100,17 @@ private:
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NonnullOwnPtr<IOWindow> m_registers_io_window;
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Spinlock m_async_lock;
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Spinlock m_schedule_lock;
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OwnPtr<UHCIRootHub> m_root_hub;
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OwnPtr<UHCIDescriptorPool<QueueHead>> m_queue_head_pool;
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OwnPtr<UHCIDescriptorPool<TransferDescriptor>> m_transfer_descriptor_pool;
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Vector<TransferDescriptor*> m_iso_td_list;
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Array<OwnPtr<AsyncTransferHandle>, MAXIMUM_NUMBER_OF_QHS> m_active_async_transfers;
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QueueHead* m_schedule_begin_anchor;
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Array<QueueHead*, NUMBER_OF_INTERRUPT_QHS> m_interrupt_qh_anchor_arr;
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QueueHead* m_interrupt_qh_anchor;
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QueueHead* m_ls_control_qh_anchor;
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QueueHead* m_fs_control_qh_anchor;
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// Always final queue in the schedule, may loop back to previous QH for bandwidth
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@ -356,6 +356,15 @@ struct alignas(16) QueueHead {
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m_bookkeeping->in_use = false;
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}
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void reinitialize()
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{
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for (TransferDescriptor* iter = get_first_td(); iter != nullptr; iter = iter->next_td()) {
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iter->set_active();
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}
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attach_transfer_descriptor_chain(get_first_td());
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}
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private:
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u32 m_link_ptr { 0 }; // Pointer to the next horizontal object that the controller will execute after this one
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volatile u32 m_element_link_ptr { 0 }; // Pointer to the first data object in the queue (can be modified by hw)
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@ -366,4 +375,11 @@ private:
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};
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static_assert(AssertSize<QueueHead, 32>()); // Queue Head is always 8 Dwords
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struct AsyncTransferHandle {
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NonnullLockRefPtr<Transfer> transfer;
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QueueHead* qh;
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u16 ms_poll_interval;
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};
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}
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@ -23,8 +23,10 @@ public:
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virtual ErrorOr<void> stop() = 0;
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virtual ErrorOr<void> start() = 0;
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virtual void cancel_async_transfer(NonnullLockRefPtr<Transfer> transfer) = 0;
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virtual ErrorOr<size_t> submit_control_transfer(Transfer&) = 0;
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virtual ErrorOr<size_t> submit_bulk_transfer(Transfer& transfer) = 0;
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virtual ErrorOr<void> submit_async_interrupt_transfer(NonnullLockRefPtr<Transfer> transfer, u16 ms_interval) = 0;
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u8 allocate_address();
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@ -50,7 +50,7 @@ ErrorOr<size_t> ControlPipe::control_transfer(u8 request_type, u8 request, u16 v
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usb_request.index = index;
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usb_request.length = length;
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auto transfer = TRY(Transfer::try_create(*this, length, *m_dma_buffer));
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auto transfer = TRY(Transfer::create(*this, length, *m_dma_buffer));
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transfer->set_setup_packet(usb_request);
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dbgln_if(USB_DEBUG, "ControlPipe: Transfer allocated @ {}", transfer->buffer_physical());
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@ -84,7 +84,7 @@ ErrorOr<size_t> BulkInPipe::bulk_in_transfer(size_t length, void* data)
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size_t transfer_length = 0;
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auto transfer = TRY(Transfer::try_create(*this, length, *m_dma_buffer));
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auto transfer = TRY(Transfer::create(*this, length, *m_dma_buffer));
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dbgln_if(USB_DEBUG, "Pipe: Bulk in transfer allocated @ {}", transfer->buffer_physical());
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transfer_length = TRY(m_controller->submit_bulk_transfer(*transfer));
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@ -114,7 +114,7 @@ ErrorOr<size_t> BulkOutPipe::bulk_out_transfer(size_t length, void* data)
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MutexLocker lock(m_dma_buffer_lock);
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size_t transfer_length = 0;
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auto transfer = TRY(Transfer::try_create(*this, length, *m_dma_buffer));
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auto transfer = TRY(Transfer::create(*this, length, *m_dma_buffer));
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TRY(transfer->write_buffer(length, data));
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dbgln_if(USB_DEBUG, "Pipe: Bulk out transfer allocated @ {}", transfer->buffer_physical());
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@ -137,6 +137,16 @@ InterruptInPipe::InterruptInPipe(USBController const& controller, u8 endpoint_ad
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{
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}
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ErrorOr<NonnullLockRefPtr<Transfer>> InterruptInPipe::interrupt_in_transfer(size_t length, u16 ms_interval, USBAsyncCallback callback)
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{
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VERIFY(length <= m_dma_buffer->size());
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auto transfer = TRY(Transfer::create(*this, length, *m_dma_buffer, move(callback)));
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dbgln_if(USB_DEBUG, "Pipe: Interrupt in transfer allocated @ {}", transfer->buffer_physical());
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TRY(m_controller->submit_async_interrupt_transfer(transfer, ms_interval));
|
||||
return transfer;
|
||||
}
|
||||
|
||||
ErrorOr<NonnullOwnPtr<InterruptOutPipe>> InterruptOutPipe::create(USBController const& controller, u8 endpoint_address, u16 max_packet_size, i8 device_address, u16 poll_interval, size_t buffer_size)
|
||||
{
|
||||
VERIFY(buffer_size >= max_packet_size);
|
||||
|
|
|
|||
|
|
@ -18,6 +18,8 @@ namespace Kernel::USB {
|
|||
class USBController;
|
||||
class Transfer;
|
||||
|
||||
using USBAsyncCallback = Function<void(Transfer* transfer)>;
|
||||
|
||||
//
|
||||
// A pipe is the logical connection between a memory buffer on the PC (host) and
|
||||
// an endpoint on the device. In this implementation, the data buffer the pipe connects
|
||||
|
|
@ -111,6 +113,8 @@ class InterruptInPipe : public Pipe {
|
|||
public:
|
||||
static ErrorOr<NonnullOwnPtr<InterruptInPipe>> create(USBController const& controller, u8 endpoint_address, u16 max_packet_size, i8 device_address, u16 poll_interval, size_t buffer_size = PAGE_SIZE);
|
||||
|
||||
ErrorOr<NonnullLockRefPtr<Transfer>> interrupt_in_transfer(size_t length, u16 ms_interval, USBAsyncCallback callback);
|
||||
|
||||
u16 poll_interval() const { return m_poll_interval; }
|
||||
|
||||
private:
|
||||
|
|
|
|||
|
|
@ -9,15 +9,16 @@
|
|||
|
||||
namespace Kernel::USB {
|
||||
|
||||
ErrorOr<NonnullLockRefPtr<Transfer>> Transfer::try_create(Pipe& pipe, u16 length, Memory::Region& dma_buffer)
|
||||
ErrorOr<NonnullLockRefPtr<Transfer>> Transfer::create(Pipe& pipe, u16 length, Memory::Region& dma_buffer, USBAsyncCallback callback)
|
||||
{
|
||||
return adopt_nonnull_lock_ref_or_enomem(new (nothrow) Transfer(pipe, length, dma_buffer));
|
||||
return adopt_nonnull_lock_ref_or_enomem(new (nothrow) Transfer(pipe, length, dma_buffer, move(callback)));
|
||||
}
|
||||
|
||||
Transfer::Transfer(Pipe& pipe, u16 len, Memory::Region& dma_buffer)
|
||||
Transfer::Transfer(Pipe& pipe, u16 len, Memory::Region& dma_buffer, USBAsyncCallback callback)
|
||||
: m_pipe(pipe)
|
||||
, m_dma_buffer(dma_buffer)
|
||||
, m_transfer_data_size(len)
|
||||
, m_callback(move(callback))
|
||||
{
|
||||
}
|
||||
|
||||
|
|
@ -49,4 +50,10 @@ ErrorOr<void> Transfer::write_buffer(u16 len, void* data)
|
|||
return {};
|
||||
}
|
||||
|
||||
void Transfer::invoke_async_callback()
|
||||
{
|
||||
if (m_callback)
|
||||
m_callback(this);
|
||||
}
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@ namespace Kernel::USB {
|
|||
|
||||
class Transfer final : public AtomicRefCounted<Transfer> {
|
||||
public:
|
||||
static ErrorOr<NonnullLockRefPtr<Transfer>> try_create(Pipe&, u16 length, Memory::Region& dma_buffer);
|
||||
static ErrorOr<NonnullLockRefPtr<Transfer>> create(Pipe&, u16 length, Memory::Region& dma_buffer, USBAsyncCallback callback = nullptr);
|
||||
|
||||
Transfer() = delete;
|
||||
~Transfer();
|
||||
|
|
@ -41,14 +41,17 @@ public:
|
|||
bool complete() const { return m_complete; }
|
||||
bool error_occurred() const { return m_error_occurred; }
|
||||
|
||||
void invoke_async_callback();
|
||||
|
||||
private:
|
||||
Transfer(Pipe& pipe, u16 len, Memory::Region& dma_buffer);
|
||||
Transfer(Pipe& pipe, u16 len, Memory::Region& dma_buffer, USBAsyncCallback callback);
|
||||
Pipe& m_pipe; // Pipe that initiated this transfer
|
||||
Memory::Region& m_dma_buffer; // DMA buffer
|
||||
USBRequestData m_request; // USB request
|
||||
u16 m_transfer_data_size { 0 }; // Size of the transfer's data stage
|
||||
bool m_complete { false }; // Has this transfer been completed?
|
||||
bool m_error_occurred { false }; // Did an error occur during this transfer?
|
||||
USBAsyncCallback m_callback { nullptr };
|
||||
};
|
||||
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue