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Kernel: Add riscv64 assembly startup code
This adds a simple boot.S for RISC-V (64-bit), which clears the BSS and sets up the processor to be ready for pre_init.cpp (which is not added yet).
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74
Kernel/Arch/riscv64/boot.S
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74
Kernel/Arch/riscv64/boot.S
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/*
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* Copyright (c) 2023, Sönke Holz <sholz830@gmail.com>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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// In a specially-named text section so that the linker script can put it first in .text.
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.section ".text.first"
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.global start
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.type start, @function
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start:
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// We expect that only one hart jumps here and that we are running in supervisor mode.
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// We also expect that an implementation of the RISC-V Supervisor Binary Interface is available.
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// Don't touch a0/a1 as we expect those registers to contain the hart ID
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// and a pointer to the Flattened Fevice Tree.
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// Set sstatus to a known state (which includes disabling supervisor interrupts).
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csrw sstatus, zero
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// Also, disable all interrupts sources and mark them as non-pending.
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csrw sie, zero
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csrw sip, zero
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// TODO: maybe load the gp register here?
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// Clear the BSS.
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lla t0, start_of_bss
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lla t1, end_of_bss
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bgeu t0, t1, Lclear_bss_done
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Lclear_bss_loop:
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sd zero, (t0)
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addi t0, t0, 8
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bltu t0, t1, Lclear_bss_loop
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Lclear_bss_done:
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// Let the stack start before .text for now.
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lla sp, start
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// Zero all registers except sp, a0 and a1.
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li ra, 0
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// sp
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li gp, 0
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li tp, 0
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li t0, 0
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li t1, 0
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li t2, 0
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li fp, 0
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li s1, 0
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// a0
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// a1
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li a2, 0
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li a3, 0
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li a4, 0
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li a5, 0
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li a6, 0
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li a7, 0
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li s2, 0
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li s3, 0
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li s4, 0
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li s5, 0
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li s6, 0
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li s7, 0
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li s8, 0
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li s9, 0
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li s10, 0
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li s11, 0
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li t3, 0
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li t4, 0
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li t5, 0
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li t6, 0
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tail pre_init
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@ -499,6 +499,7 @@ elseif("${SERENITY_ARCH}" STREQUAL "aarch64")
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elseif("${SERENITY_ARCH}" STREQUAL "riscv64")
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set(KERNEL_SOURCES
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${KERNEL_SOURCES}
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Arch/riscv64/boot.S
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Arch/Processor.cpp
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kprintf.cpp
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)
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