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Kernel/riscv64: Add RISC-V support to TimeManagement
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@ -19,6 +19,7 @@
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#elif ARCH(AARCH64)
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# include <Kernel/Arch/aarch64/RPi/Timer.h>
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#elif ARCH(RISCV64)
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# include <Kernel/Arch/riscv64/Timer.h>
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#else
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# error Unknown architecture
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#endif
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@ -207,7 +208,10 @@ UNMAP_AFTER_INIT void TimeManagement::initialize([[maybe_unused]] u32 cpu)
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s_the.ensure_instance();
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}
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#elif ARCH(RISCV64)
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TODO_RISCV64();
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if (cpu == 0) {
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VERIFY(!s_the.is_initialized());
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s_the.ensure_instance();
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}
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#else
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# error Unknown architecture
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#endif
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@ -484,7 +488,31 @@ UNMAP_AFTER_INIT bool TimeManagement::probe_and_set_aarch64_hardware_timers()
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#elif ARCH(RISCV64)
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UNMAP_AFTER_INIT bool TimeManagement::probe_and_set_riscv64_hardware_timers()
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{
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TODO_RISCV64();
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m_hardware_timers.append(RISCV64::Timer::initialize());
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m_system_timer = m_hardware_timers[0];
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m_time_ticks_per_second = m_system_timer->frequency();
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m_system_timer->set_callback([this](RegisterState const& regs) {
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auto seconds_since_boot = m_seconds_since_boot;
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auto ticks_this_second = m_ticks_this_second;
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auto delta_ns = static_cast<RISCV64::Timer*>(m_system_timer.ptr())->update_time(seconds_since_boot, ticks_this_second, false);
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u32 update_iteration = m_update2.fetch_add(1, AK::MemoryOrder::memory_order_acquire);
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m_seconds_since_boot = seconds_since_boot;
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m_ticks_this_second = ticks_this_second;
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m_epoch_time += Duration::from_nanoseconds(delta_ns);
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m_update1.store(update_iteration + 1, AK::MemoryOrder::memory_order_release);
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update_time_page();
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system_timer_tick(regs);
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});
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m_time_keeper_timer = m_system_timer;
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return true;
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}
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#else
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# error Unknown architecture
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