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https://github.com/SerenityOS/serenity
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NVMe: Use an explicit Queue type instead of using an Optional irq
Add an explicit QueueType enum which could be used to create a poll or an interrupt queue. This is better than passing an Optional<irq>. This refactoring is in preparation for adding MSIx support to NVMe.
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@ -36,7 +36,7 @@ UNMAP_AFTER_INIT ErrorOr<void> NVMeController::initialize(bool is_queue_polled)
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{
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// Nr of queues = one queue per core
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auto nr_of_queues = Processor::count();
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auto irq = is_queue_polled ? Optional<u8> {} : device_identifier().interrupt_line().value();
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auto queue_type = is_queue_polled ? QueueType::Polled : QueueType::IRQ;
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PCI::enable_memory_space(device_identifier());
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PCI::enable_bus_mastering(device_identifier());
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@ -52,7 +52,7 @@ UNMAP_AFTER_INIT ErrorOr<void> NVMeController::initialize(bool is_queue_polled)
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m_ready_timeout = Time::from_milliseconds((CAP_TO(caps) + 1) * 500); // CAP.TO is in 500ms units
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calculate_doorbell_stride();
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TRY(create_admin_queue(irq));
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TRY(create_admin_queue(queue_type));
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VERIFY(m_admin_queue_ready == true);
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VERIFY(IO_QUEUE_SIZE < MQES(caps));
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@ -61,7 +61,7 @@ UNMAP_AFTER_INIT ErrorOr<void> NVMeController::initialize(bool is_queue_polled)
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// Create an IO queue per core
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for (u32 cpuid = 0; cpuid < nr_of_queues; ++cpuid) {
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// qid is zero is used for admin queue
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TRY(create_io_queue(cpuid + 1, irq));
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TRY(create_io_queue(cpuid + 1, queue_type));
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}
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TRY(identify_and_init_namespaces());
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return {};
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@ -249,7 +249,7 @@ void NVMeController::complete_current_request([[maybe_unused]] AsyncDeviceReques
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VERIFY_NOT_REACHED();
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}
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UNMAP_AFTER_INIT ErrorOr<void> NVMeController::create_admin_queue(Optional<u8> irq)
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UNMAP_AFTER_INIT ErrorOr<void> NVMeController::create_admin_queue(QueueType queue_type)
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{
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auto qdepth = get_admin_q_dept();
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OwnPtr<Memory::Region> cq_dma_region;
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@ -287,13 +287,13 @@ UNMAP_AFTER_INIT ErrorOr<void> NVMeController::create_admin_queue(Optional<u8> i
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return maybe_error;
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}
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set_admin_queue_ready_flag();
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m_admin_queue = TRY(NVMeQueue::try_create(0, irq, qdepth, move(cq_dma_region), cq_dma_pages, move(sq_dma_region), sq_dma_pages, move(doorbell_regs)));
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m_admin_queue = TRY(NVMeQueue::try_create(0, device_identifier().interrupt_line().value(), qdepth, move(cq_dma_region), cq_dma_pages, move(sq_dma_region), sq_dma_pages, move(doorbell_regs), queue_type));
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dbgln_if(NVME_DEBUG, "NVMe: Admin queue created");
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return {};
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}
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UNMAP_AFTER_INIT ErrorOr<void> NVMeController::create_io_queue(u8 qid, Optional<u8> irq)
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UNMAP_AFTER_INIT ErrorOr<void> NVMeController::create_io_queue(u8 qid, QueueType queue_type)
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{
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OwnPtr<Memory::Region> cq_dma_region;
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Vector<NonnullRefPtr<Memory::PhysicalPage>> cq_dma_pages;
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@ -323,7 +323,7 @@ UNMAP_AFTER_INIT ErrorOr<void> NVMeController::create_io_queue(u8 qid, Optional<
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sub.create_cq.cqid = qid;
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// The queue size is 0 based
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sub.create_cq.qsize = AK::convert_between_host_and_little_endian(IO_QUEUE_SIZE - 1);
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auto flags = irq.has_value() ? QUEUE_IRQ_ENABLED : QUEUE_IRQ_DISABLED;
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auto flags = (queue_type == QueueType::IRQ) ? QUEUE_IRQ_ENABLED : QUEUE_IRQ_DISABLED;
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flags |= QUEUE_PHY_CONTIGUOUS;
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// TODO: Eventually move to MSI.
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// For now using pin based interrupts. Clear the first 16 bits
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@ -347,7 +347,7 @@ UNMAP_AFTER_INIT ErrorOr<void> NVMeController::create_io_queue(u8 qid, Optional<
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auto queue_doorbell_offset = REG_SQ0TDBL_START + ((2 * qid) * (4 << m_dbl_stride));
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auto doorbell_regs = TRY(Memory::map_typed_writable<DoorbellRegister volatile>(PhysicalAddress(m_bar + queue_doorbell_offset)));
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m_queues.append(TRY(NVMeQueue::try_create(qid, irq, IO_QUEUE_SIZE, move(cq_dma_region), cq_dma_pages, move(sq_dma_region), sq_dma_pages, move(doorbell_regs))));
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m_queues.append(TRY(NVMeQueue::try_create(qid, device_identifier().interrupt_line().value(), IO_QUEUE_SIZE, move(cq_dma_region), cq_dma_pages, move(sq_dma_region), sq_dma_pages, move(doorbell_regs), queue_type)));
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dbgln_if(NVME_DEBUG, "NVMe: Created IO Queue with QID{}", m_queues.size());
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return {};
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}
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@ -59,8 +59,8 @@ private:
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ErrorOr<void> identify_and_init_namespaces();
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Tuple<u64, u8> get_ns_features(IdentifyNamespace& identify_data_struct);
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ErrorOr<void> create_admin_queue(Optional<u8> irq);
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ErrorOr<void> create_io_queue(u8 qid, Optional<u8> irq);
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ErrorOr<void> create_admin_queue(QueueType queue_type);
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ErrorOr<void> create_io_queue(u8 qid, QueueType queue_type);
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void calculate_doorbell_stride()
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{
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m_dbl_stride = (m_controller_regs->cap >> CAP_DBL_SHIFT) & CAP_DBL_MASK;
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@ -77,6 +77,7 @@ private:
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AK::Time m_ready_timeout;
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u32 m_bar { 0 };
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u8 m_dbl_stride { 0 };
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QueueType m_queue_type { QueueType::IRQ };
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static Atomic<u8> s_controller_id;
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};
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}
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@ -12,16 +12,16 @@
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#include <Kernel/Storage/NVMe/NVMeQueue.h>
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namespace Kernel {
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ErrorOr<NonnullLockRefPtr<NVMeQueue>> NVMeQueue::try_create(u16 qid, Optional<u8> irq, u32 q_depth, OwnPtr<Memory::Region> cq_dma_region, Vector<NonnullRefPtr<Memory::PhysicalPage>> cq_dma_page, OwnPtr<Memory::Region> sq_dma_region, Vector<NonnullRefPtr<Memory::PhysicalPage>> sq_dma_page, Memory::TypedMapping<DoorbellRegister volatile> db_regs)
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ErrorOr<NonnullLockRefPtr<NVMeQueue>> NVMeQueue::try_create(u16 qid, u8 irq, u32 q_depth, OwnPtr<Memory::Region> cq_dma_region, Vector<NonnullRefPtr<Memory::PhysicalPage>> cq_dma_page, OwnPtr<Memory::Region> sq_dma_region, Vector<NonnullRefPtr<Memory::PhysicalPage>> sq_dma_page, Memory::TypedMapping<DoorbellRegister volatile> db_regs, QueueType queue_type)
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{
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// Note: Allocate DMA region for RW operation. For now the requests don't exceed more than 4096 bytes (Storage device takes care of it)
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RefPtr<Memory::PhysicalPage> rw_dma_page;
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auto rw_dma_region = TRY(MM.allocate_dma_buffer_page("NVMe Queue Read/Write DMA"sv, Memory::Region::Access::ReadWrite, rw_dma_page));
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if (!irq.has_value()) {
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if (queue_type == QueueType::Polled) {
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auto queue = TRY(adopt_nonnull_lock_ref_or_enomem(new (nothrow) NVMePollQueue(move(rw_dma_region), *rw_dma_page, qid, q_depth, move(cq_dma_region), cq_dma_page, move(sq_dma_region), sq_dma_page, move(db_regs))));
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return queue;
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}
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auto queue = TRY(adopt_nonnull_lock_ref_or_enomem(new (nothrow) NVMeInterruptQueue(move(rw_dma_region), *rw_dma_page, qid, irq.value(), q_depth, move(cq_dma_region), cq_dma_page, move(sq_dma_region), sq_dma_page, move(db_regs))));
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auto queue = TRY(adopt_nonnull_lock_ref_or_enomem(new (nothrow) NVMeInterruptQueue(move(rw_dma_region), *rw_dma_page, qid, irq, q_depth, move(cq_dma_region), cq_dma_page, move(sq_dma_region), sq_dma_page, move(db_regs))));
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return queue;
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}
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@ -26,6 +26,11 @@ struct DoorbellRegister {
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u32 cq_head;
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};
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enum class QueueType {
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Polled,
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IRQ
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};
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class AsyncBlockDeviceRequest;
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struct NVMeIO {
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@ -36,7 +41,7 @@ struct NVMeIO {
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class NVMeQueue : public AtomicRefCounted<NVMeQueue> {
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public:
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static ErrorOr<NonnullLockRefPtr<NVMeQueue>> try_create(u16 qid, Optional<u8> irq, u32 q_depth, OwnPtr<Memory::Region> cq_dma_region, Vector<NonnullRefPtr<Memory::PhysicalPage>> cq_dma_page, OwnPtr<Memory::Region> sq_dma_region, Vector<NonnullRefPtr<Memory::PhysicalPage>> sq_dma_page, Memory::TypedMapping<DoorbellRegister volatile> db_regs);
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static ErrorOr<NonnullLockRefPtr<NVMeQueue>> try_create(u16 qid, u8 irq, u32 q_depth, OwnPtr<Memory::Region> cq_dma_region, Vector<NonnullRefPtr<Memory::PhysicalPage>> cq_dma_page, OwnPtr<Memory::Region> sq_dma_region, Vector<NonnullRefPtr<Memory::PhysicalPage>> sq_dma_page, Memory::TypedMapping<DoorbellRegister volatile> db_regs, QueueType queue_type);
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bool is_admin_queue() { return m_admin_queue; };
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u16 submit_sync_sqe(NVMeSubmission&);
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void read(AsyncBlockDeviceRequest& request, u16 nsid, u64 index, u32 count);
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