From 57901a6f62dbf1cdac577eb0d43004e547e337c3 Mon Sep 17 00:00:00 2001 From: Timon Kruiper Date: Wed, 21 Sep 2022 09:24:56 +0200 Subject: [PATCH] Kernel/aarch64: Implement tlb flushing This initial implementation flushes the complete tlb cache. A FIXME is added to implement the partial tlb flushing. --- Kernel/Arch/aarch64/Processor.cpp | 11 ++++++++++- Kernel/Arch/aarch64/Processor.h | 5 +---- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/Kernel/Arch/aarch64/Processor.cpp b/Kernel/Arch/aarch64/Processor.cpp index f61d4f0b30..daf2917567 100644 --- a/Kernel/Arch/aarch64/Processor.cpp +++ b/Kernel/Arch/aarch64/Processor.cpp @@ -41,7 +41,16 @@ void Processor::initialize(u32 cpu) void Processor::flush_tlb_local(VirtualAddress, size_t) { - // FIXME: Implement this + // FIXME: Figure out how to flush a single page + asm volatile("dsb ishst"); + asm volatile("tlbi vmalle1is"); + asm volatile("dsb ish"); + asm volatile("isb"); +} + +void Processor::flush_tlb(Memory::PageDirectory const*, VirtualAddress vaddr, size_t page_count) +{ + flush_tlb_local(vaddr, page_count); } } diff --git a/Kernel/Arch/aarch64/Processor.h b/Kernel/Arch/aarch64/Processor.h index a6e93d8dbd..163d5815ad 100644 --- a/Kernel/Arch/aarch64/Processor.h +++ b/Kernel/Arch/aarch64/Processor.h @@ -77,10 +77,7 @@ public: } static void flush_tlb_local(VirtualAddress vaddr, size_t page_count); - ALWAYS_INLINE static void flush_tlb(Memory::PageDirectory const*, VirtualAddress const&, size_t) - { - VERIFY_NOT_REACHED(); - } + static void flush_tlb(Memory::PageDirectory const*, VirtualAddress, size_t); // FIXME: When aarch64 supports multiple cores, return the correct core id here. ALWAYS_INLINE static u32 current_id()