mirror of
https://gitlab.com/qemu-project/qemu
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276 lines
7.4 KiB
C
276 lines
7.4 KiB
C
/*
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* Softmmu related functions
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*
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* Copyright (C) 2010-2012 Guan Xuetao
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation, or any later version.
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* See the COPYING file in the top-level directory.
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*/
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#ifdef CONFIG_USER_ONLY
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#error This file only exist under softmmu circumstance
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#endif
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#include <cpu.h>
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#undef DEBUG_UC32
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#ifdef DEBUG_UC32
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#define DPRINTF(fmt, ...) printf("%s: " fmt , __func__, ## __VA_ARGS__)
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#else
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#define DPRINTF(fmt, ...) do {} while (0)
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#endif
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#define SUPERPAGE_SIZE (1 << 22)
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#define UC32_PAGETABLE_READ (1 << 8)
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#define UC32_PAGETABLE_WRITE (1 << 7)
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#define UC32_PAGETABLE_EXEC (1 << 6)
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#define UC32_PAGETABLE_EXIST (1 << 2)
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#define PAGETABLE_TYPE(x) ((x) & 3)
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/* Map CPU modes onto saved register banks. */
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static inline int bank_number(CPUUniCore32State *env, int mode)
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{
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UniCore32CPU *cpu = uc32_env_get_cpu(env);
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switch (mode) {
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case ASR_MODE_USER:
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case ASR_MODE_SUSR:
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return 0;
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case ASR_MODE_PRIV:
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return 1;
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case ASR_MODE_TRAP:
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return 2;
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case ASR_MODE_EXTN:
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return 3;
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case ASR_MODE_INTR:
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return 4;
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}
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cpu_abort(CPU(cpu), "Bad mode %x\n", mode);
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return -1;
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}
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void switch_mode(CPUUniCore32State *env, int mode)
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{
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int old_mode;
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int i;
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old_mode = env->uncached_asr & ASR_M;
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if (mode == old_mode) {
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return;
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}
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i = bank_number(env, old_mode);
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env->banked_r29[i] = env->regs[29];
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env->banked_r30[i] = env->regs[30];
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env->banked_bsr[i] = env->bsr;
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i = bank_number(env, mode);
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env->regs[29] = env->banked_r29[i];
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env->regs[30] = env->banked_r30[i];
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env->bsr = env->banked_bsr[i];
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}
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/* Handle a CPU exception. */
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void uc32_cpu_do_interrupt(CPUState *cs)
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{
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UniCore32CPU *cpu = UNICORE32_CPU(cs);
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CPUUniCore32State *env = &cpu->env;
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uint32_t addr;
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int new_mode;
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switch (cs->exception_index) {
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case UC32_EXCP_PRIV:
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new_mode = ASR_MODE_PRIV;
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addr = 0x08;
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break;
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case UC32_EXCP_ITRAP:
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DPRINTF("itrap happened at %x\n", env->regs[31]);
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new_mode = ASR_MODE_TRAP;
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addr = 0x0c;
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break;
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case UC32_EXCP_DTRAP:
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DPRINTF("dtrap happened at %x\n", env->regs[31]);
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new_mode = ASR_MODE_TRAP;
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addr = 0x10;
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break;
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case UC32_EXCP_INTR:
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new_mode = ASR_MODE_INTR;
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addr = 0x18;
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break;
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default:
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cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
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return;
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}
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/* High vectors. */
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if (env->cp0.c1_sys & (1 << 13)) {
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addr += 0xffff0000;
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}
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switch_mode(env, new_mode);
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env->bsr = cpu_asr_read(env);
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env->uncached_asr = (env->uncached_asr & ~ASR_M) | new_mode;
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env->uncached_asr |= ASR_I;
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/* The PC already points to the proper instruction. */
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env->regs[30] = env->regs[31];
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env->regs[31] = addr;
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cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
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}
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static int get_phys_addr_ucv2(CPUUniCore32State *env, uint32_t address,
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int access_type, int is_user, uint32_t *phys_ptr, int *prot,
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target_ulong *page_size)
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{
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UniCore32CPU *cpu = uc32_env_get_cpu(env);
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CPUState *cs = CPU(cpu);
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int code;
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uint32_t table;
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uint32_t desc;
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uint32_t phys_addr;
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/* Pagetable walk. */
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/* Lookup l1 descriptor. */
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table = env->cp0.c2_base & 0xfffff000;
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table |= (address >> 20) & 0xffc;
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desc = ldl_phys(cs->as, table);
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code = 0;
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switch (PAGETABLE_TYPE(desc)) {
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case 3:
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/* Superpage */
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if (!(desc & UC32_PAGETABLE_EXIST)) {
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code = 0x0b; /* superpage miss */
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goto do_fault;
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}
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phys_addr = (desc & 0xffc00000) | (address & 0x003fffff);
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*page_size = SUPERPAGE_SIZE;
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break;
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case 0:
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/* Lookup l2 entry. */
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if (is_user) {
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DPRINTF("PGD address %x, desc %x\n", table, desc);
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}
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if (!(desc & UC32_PAGETABLE_EXIST)) {
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code = 0x05; /* second pagetable miss */
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goto do_fault;
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}
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table = (desc & 0xfffff000) | ((address >> 10) & 0xffc);
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desc = ldl_phys(cs->as, table);
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/* 4k page. */
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if (is_user) {
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DPRINTF("PTE address %x, desc %x\n", table, desc);
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}
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if (!(desc & UC32_PAGETABLE_EXIST)) {
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code = 0x08; /* page miss */
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goto do_fault;
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}
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switch (PAGETABLE_TYPE(desc)) {
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case 0:
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phys_addr = (desc & 0xfffff000) | (address & 0xfff);
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*page_size = TARGET_PAGE_SIZE;
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break;
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default:
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cpu_abort(CPU(cpu), "wrong page type!");
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}
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break;
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default:
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cpu_abort(CPU(cpu), "wrong page type!");
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}
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*phys_ptr = phys_addr;
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*prot = 0;
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/* Check access permissions. */
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if (desc & UC32_PAGETABLE_READ) {
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*prot |= PAGE_READ;
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} else {
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if (is_user && (access_type == 0)) {
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code = 0x11; /* access unreadable area */
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goto do_fault;
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}
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}
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if (desc & UC32_PAGETABLE_WRITE) {
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*prot |= PAGE_WRITE;
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} else {
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if (is_user && (access_type == 1)) {
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code = 0x12; /* access unwritable area */
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goto do_fault;
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}
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}
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if (desc & UC32_PAGETABLE_EXEC) {
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*prot |= PAGE_EXEC;
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} else {
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if (is_user && (access_type == 2)) {
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code = 0x13; /* access unexecutable area */
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goto do_fault;
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}
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}
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do_fault:
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return code;
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}
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int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
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int access_type, int mmu_idx)
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{
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UniCore32CPU *cpu = UNICORE32_CPU(cs);
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CPUUniCore32State *env = &cpu->env;
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uint32_t phys_addr;
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target_ulong page_size;
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int prot;
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int ret, is_user;
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ret = 1;
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is_user = mmu_idx == MMU_USER_IDX;
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if ((env->cp0.c1_sys & 1) == 0) {
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/* MMU disabled. */
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phys_addr = address;
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prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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page_size = TARGET_PAGE_SIZE;
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ret = 0;
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} else {
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if ((address & (1 << 31)) || (is_user)) {
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ret = get_phys_addr_ucv2(env, address, access_type, is_user,
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&phys_addr, &prot, &page_size);
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if (is_user) {
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DPRINTF("user space access: ret %x, address %" VADDR_PRIx ", "
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"access_type %x, phys_addr %x, prot %x\n",
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ret, address, access_type, phys_addr, prot);
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}
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} else {
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/*IO memory */
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phys_addr = address | (1 << 31);
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prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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page_size = TARGET_PAGE_SIZE;
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ret = 0;
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}
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}
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if (ret == 0) {
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/* Map a single page. */
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phys_addr &= TARGET_PAGE_MASK;
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address &= TARGET_PAGE_MASK;
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tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size);
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return 0;
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}
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env->cp0.c3_faultstatus = ret;
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env->cp0.c4_faultaddr = address;
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if (access_type == 2) {
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cs->exception_index = UC32_EXCP_ITRAP;
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} else {
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cs->exception_index = UC32_EXCP_DTRAP;
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}
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return ret;
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}
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hwaddr uc32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
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{
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UniCore32CPU *cpu = UNICORE32_CPU(cs);
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cpu_abort(CPU(cpu), "%s not supported yet\n", __func__);
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return addr;
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}
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