mirror of
https://gitlab.com/qemu-project/qemu
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3ec0fe18a3
vstimecmp CSR allows the guest OS or to program the next guest timer interrupt directly. Thus, hypervisor no longer need to inject the timer interrupt to the guest if vstimecmp is used. This was ratified as a part of the Sstc extension. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220824221357.41070-4-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
115 lines
3.4 KiB
C
115 lines
3.4 KiB
C
/*
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* RISC-V timer helper implementation.
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*
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* Copyright (c) 2022 Rivos Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "cpu_bits.h"
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#include "time_helper.h"
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#include "hw/intc/riscv_aclint.h"
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static void riscv_vstimer_cb(void *opaque)
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{
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RISCVCPU *cpu = opaque;
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CPURISCVState *env = &cpu->env;
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env->vstime_irq = 1;
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riscv_cpu_update_mip(cpu, MIP_VSTIP, BOOL_TO_MASK(1));
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}
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static void riscv_stimer_cb(void *opaque)
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{
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RISCVCPU *cpu = opaque;
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riscv_cpu_update_mip(cpu, MIP_STIP, BOOL_TO_MASK(1));
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}
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/*
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* Called when timecmp is written to update the QEMU timer or immediately
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* trigger timer interrupt if mtimecmp <= current timer value.
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*/
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void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer,
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uint64_t timecmp, uint64_t delta,
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uint32_t timer_irq)
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{
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uint64_t diff, ns_diff, next;
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CPURISCVState *env = &cpu->env;
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RISCVAclintMTimerState *mtimer = env->rdtime_fn_arg;
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uint32_t timebase_freq = mtimer->timebase_freq;
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uint64_t rtc_r = env->rdtime_fn(env->rdtime_fn_arg) + delta;
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if (timecmp <= rtc_r) {
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/*
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* If we're setting an stimecmp value in the "past",
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* immediately raise the timer interrupt
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*/
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if (timer_irq == MIP_VSTIP) {
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env->vstime_irq = 1;
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}
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riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(1));
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return;
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}
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if (timer_irq == MIP_VSTIP) {
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env->vstime_irq = 0;
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}
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/* Clear the [V]STIP bit in mip */
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riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0));
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/* otherwise, set up the future timer interrupt */
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diff = timecmp - rtc_r;
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/* back to ns (note args switched in muldiv64) */
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ns_diff = muldiv64(diff, NANOSECONDS_PER_SECOND, timebase_freq);
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/*
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* check if ns_diff overflowed and check if the addition would potentially
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* overflow
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*/
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if ((NANOSECONDS_PER_SECOND > timebase_freq && ns_diff < diff) ||
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ns_diff > INT64_MAX) {
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next = INT64_MAX;
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} else {
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/*
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* as it is very unlikely qemu_clock_get_ns will return a value
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* greater than INT64_MAX, no additional check is needed for an
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* unsigned integer overflow.
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*/
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next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + ns_diff;
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/*
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* if ns_diff is INT64_MAX next may still be outside the range
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* of a signed integer.
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*/
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next = MIN(next, INT64_MAX);
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}
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timer_mod(timer, next);
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}
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void riscv_timer_init(RISCVCPU *cpu)
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{
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CPURISCVState *env;
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if (!cpu) {
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return;
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}
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env = &cpu->env;
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env->stimer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &riscv_stimer_cb, cpu);
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env->stimecmp = 0;
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env->vstimer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &riscv_vstimer_cb, cpu);
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env->vstimecmp = 0;
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}
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