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7da2fb240f
Add basic ACPI infrastructure for RISC-V with below tables.
1) DSDT with below basic objects
- CPUs
- fw_cfg
2) FADT revision 6 with HW_REDUCED flag
3) XSDT
4) RSDP
Add this functionality in a new file virt-acpi-build.c and enable
building this infrastructure.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230302091212.999767-5-sunilvl@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
14 lines
751 B
Meson
14 lines
751 B
Meson
riscv_ss = ss.source_set()
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riscv_ss.add(files('boot.c'), fdt)
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riscv_ss.add(when: 'CONFIG_RISCV_NUMA', if_true: files('numa.c'))
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riscv_ss.add(files('riscv_hart.c'))
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riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
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riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
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riscv_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c'))
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riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
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riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
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riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
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riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
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riscv_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c'))
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hw_arch += {'riscv': riscv_ss}
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