qemu/target-tricore
Bastian Koppelmann f69c24e458 target-tricore: properly fix dvinit_b/h_13
The TriCore documentation was wrong on how to calculate ovf bits for those two
instructions, which I confirmed with real hardware (TC1796 chip). An ovf
actually happens, if the result (without remainder) does not fit into 8/16 bits.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-03-24 09:45:28 +01:00
..
cpu-qom.h target-tricore: Remove the dummy interrupt boilerplate 2014-09-25 18:54:22 +01:00
cpu.c target-tricore: Several translator and cpu model fixes 2015-01-26 19:56:45 +00:00
cpu.h target-tricore: Add instructions of SYS opcode format 2015-03-16 15:53:08 +00:00
csfr.def target-tricore: Fix new typos 2015-01-15 10:44:13 +03:00
helper.c target-tricore: Remove the dummy interrupt boilerplate 2014-09-25 18:54:22 +01:00
helper.h target-tricore: Add instructions of SYS opcode format 2015-03-16 15:53:08 +00:00
Makefile.objs
op_helper.c target-tricore: properly fix dvinit_b/h_13 2015-03-24 09:45:28 +01:00
translate.c target-tricore: fix RRPW_DEXTR using wrong reg 2015-03-24 09:45:28 +01:00
tricore-defs.h
tricore-opcodes.h target-tricore: Add instructions of RRR1 opcode format, which have 0xe3 as first opcode 2015-03-16 15:44:48 +00:00