mirror of
https://gitlab.com/qemu-project/qemu
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477ba62001
A few words about design choices: * On IA64, instructions should be grouped by bundle, and dependencies between instructions declared. A first version of this code tried to schedule instructions automatically, but was very complex and too invasive for the current common TCG code (ops not ending at instruction boundaries, code retranslation breaking already generated code, etc.) It was also not very efficient, as dependencies between TCG ops is not available. Instead the option taken by the current implementation does not try to fill the bundle by scheduling instructions, but by providing ops not available as an ia64 instruction, and by offering 22-bit constant loading for most of the instructions. With both options the bundle are filled at approximately the same level. * Up to 128 registers can be affected to a function on IA64, but TCG limits this number to 64, which is actually more than enough. The register affectation is the following: - r0: used to map a constant argument with value 0 - r1: global pointer - r2, r3: internal use - r4 to r6: not used to avoid saving them - r7: env structure - r8 to r11: free for TCG (call clobbered) - r12: stack pointer - r13: thread pointer - r14 to r31: free for TCG (call clobbered) - r32: reserved (return address) - r33: reserved (PFS) - r33 to r63: free for TCG * The IA64 architecture has only 64-bit registers and no 32-bit instructions (the only exception being cmp4). Therefore 64-bit registers and instructions are used for 32-bit ops. The adopted strategy is the same as the ABI, that is the higher 32 bits are undefined. Most ops (and, or, add, shl, etc.) can directly use the 64-bit registers, while some others have to sign-extend (sar, div, etc.) or zero-extend (shr, divu, etc.) the register first. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
124 lines
4.8 KiB
C
124 lines
4.8 KiB
C
#ifndef CPU_COMMON_H
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#define CPU_COMMON_H 1
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/* CPU interfaces that are target indpendent. */
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#if defined(__arm__) || defined(__sparc__) || defined(__mips__) || defined(__hppa__) || defined(__ia64__)
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#define WORDS_ALIGNED
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#endif
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#include "bswap.h"
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#include "qemu-queue.h"
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#if !defined(CONFIG_USER_ONLY)
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/* address in the RAM (different from a physical address) */
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typedef unsigned long ram_addr_t;
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/* memory API */
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typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value);
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typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
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void cpu_register_physical_memory_offset(target_phys_addr_t start_addr,
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ram_addr_t size,
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ram_addr_t phys_offset,
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ram_addr_t region_offset);
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static inline void cpu_register_physical_memory(target_phys_addr_t start_addr,
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ram_addr_t size,
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ram_addr_t phys_offset)
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{
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cpu_register_physical_memory_offset(start_addr, size, phys_offset, 0);
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}
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ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr);
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ram_addr_t qemu_ram_alloc(ram_addr_t);
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void qemu_ram_free(ram_addr_t addr);
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/* This should only be used for ram local to a device. */
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void *qemu_get_ram_ptr(ram_addr_t addr);
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/* This should not be used by devices. */
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ram_addr_t qemu_ram_addr_from_host(void *ptr);
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int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read,
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CPUWriteMemoryFunc * const *mem_write,
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void *opaque);
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void cpu_unregister_io_memory(int table_address);
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void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
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int len, int is_write);
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static inline void cpu_physical_memory_read(target_phys_addr_t addr,
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uint8_t *buf, int len)
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{
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cpu_physical_memory_rw(addr, buf, len, 0);
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}
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static inline void cpu_physical_memory_write(target_phys_addr_t addr,
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const uint8_t *buf, int len)
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{
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cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1);
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}
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void *cpu_physical_memory_map(target_phys_addr_t addr,
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target_phys_addr_t *plen,
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int is_write);
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void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len,
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int is_write, target_phys_addr_t access_len);
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void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque));
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void cpu_unregister_map_client(void *cookie);
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struct CPUPhysMemoryClient;
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typedef struct CPUPhysMemoryClient CPUPhysMemoryClient;
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struct CPUPhysMemoryClient {
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void (*set_memory)(struct CPUPhysMemoryClient *client,
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target_phys_addr_t start_addr,
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ram_addr_t size,
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ram_addr_t phys_offset);
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int (*sync_dirty_bitmap)(struct CPUPhysMemoryClient *client,
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target_phys_addr_t start_addr,
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target_phys_addr_t end_addr);
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int (*migration_log)(struct CPUPhysMemoryClient *client,
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int enable);
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QLIST_ENTRY(CPUPhysMemoryClient) list;
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};
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void cpu_register_phys_memory_client(CPUPhysMemoryClient *);
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void cpu_unregister_phys_memory_client(CPUPhysMemoryClient *);
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/* Coalesced MMIO regions are areas where write operations can be reordered.
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* This usually implies that write operations are side-effect free. This allows
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* batching which can make a major impact on performance when using
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* virtualization.
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*/
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void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
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void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
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void qemu_flush_coalesced_mmio_buffer(void);
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uint32_t ldub_phys(target_phys_addr_t addr);
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uint32_t lduw_phys(target_phys_addr_t addr);
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uint32_t ldl_phys(target_phys_addr_t addr);
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uint64_t ldq_phys(target_phys_addr_t addr);
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void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
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void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val);
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void stb_phys(target_phys_addr_t addr, uint32_t val);
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void stw_phys(target_phys_addr_t addr, uint32_t val);
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void stl_phys(target_phys_addr_t addr, uint32_t val);
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void stq_phys(target_phys_addr_t addr, uint64_t val);
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void cpu_physical_memory_write_rom(target_phys_addr_t addr,
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const uint8_t *buf, int len);
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#define IO_MEM_SHIFT 3
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#define IO_MEM_RAM (0 << IO_MEM_SHIFT) /* hardcoded offset */
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#define IO_MEM_ROM (1 << IO_MEM_SHIFT) /* hardcoded offset */
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#define IO_MEM_UNASSIGNED (2 << IO_MEM_SHIFT)
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#define IO_MEM_NOTDIRTY (3 << IO_MEM_SHIFT)
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/* Acts like a ROM when read and like a device when written. */
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#define IO_MEM_ROMD (1)
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#define IO_MEM_SUBPAGE (2)
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#define IO_MEM_SUBWIDTH (4)
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#endif
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#endif /* !CPU_COMMON_H */
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