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The license is the 'GNU General Public License v2.0 or later', not 'and': This program is free software; you can redistribute it and/ori modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. Fix the license comment. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200312213455.15854-1-philmd@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
353 lines
12 KiB
C
353 lines
12 KiB
C
/*
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* Raspberry Pi emulation (c) 2012 Gregory Estrade
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* Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous
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*
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* Rasperry Pi 2 emulation Copyright (c) 2015, Microsoft
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* Written by Andrew Baumann
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*
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* Raspberry Pi 3 emulation Copyright (c) 2018 Zoltán Baldaszti
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* Upstream code cleanup (c) 2018 Pekka Enberg
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qemu/cutils.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "hw/arm/bcm2836.h"
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#include "hw/registerfields.h"
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#include "qemu/error-report.h"
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#include "hw/boards.h"
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#include "hw/loader.h"
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#include "hw/arm/boot.h"
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#include "sysemu/sysemu.h"
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#define SMPBOOT_ADDR 0x300 /* this should leave enough space for ATAGS */
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#define MVBAR_ADDR 0x400 /* secure vectors */
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#define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */
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#define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */
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#define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */
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#define SPINTABLE_ADDR 0xd8 /* Pi 3 bootloader spintable */
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/* Registered machine type (matches RPi Foundation bootloader and U-Boot) */
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#define MACH_TYPE_BCM2708 3138
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typedef struct RaspiMachineState {
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/*< private >*/
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MachineState parent_obj;
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/*< public >*/
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BCM283XState soc;
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} RaspiMachineState;
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typedef struct RaspiMachineClass {
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/*< private >*/
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MachineClass parent_obj;
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/*< public >*/
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uint32_t board_rev;
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} RaspiMachineClass;
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#define TYPE_RASPI_MACHINE MACHINE_TYPE_NAME("raspi-common")
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#define RASPI_MACHINE(obj) \
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OBJECT_CHECK(RaspiMachineState, (obj), TYPE_RASPI_MACHINE)
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#define RASPI_MACHINE_CLASS(klass) \
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OBJECT_CLASS_CHECK(RaspiMachineClass, (klass), TYPE_RASPI_MACHINE)
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#define RASPI_MACHINE_GET_CLASS(obj) \
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OBJECT_GET_CLASS(RaspiMachineClass, (obj), TYPE_RASPI_MACHINE)
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/*
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* Board revision codes:
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* www.raspberrypi.org/documentation/hardware/raspberrypi/revision-codes/
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*/
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FIELD(REV_CODE, REVISION, 0, 4);
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FIELD(REV_CODE, TYPE, 4, 8);
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FIELD(REV_CODE, PROCESSOR, 12, 4);
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FIELD(REV_CODE, MANUFACTURER, 16, 4);
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FIELD(REV_CODE, MEMORY_SIZE, 20, 3);
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FIELD(REV_CODE, STYLE, 23, 1);
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static uint64_t board_ram_size(uint32_t board_rev)
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{
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assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */
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return 256 * MiB << FIELD_EX32(board_rev, REV_CODE, MEMORY_SIZE);
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}
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static int board_processor_id(uint32_t board_rev)
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{
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assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */
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return FIELD_EX32(board_rev, REV_CODE, PROCESSOR);
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}
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static int board_version(uint32_t board_rev)
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{
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return board_processor_id(board_rev) + 1;
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}
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static const char *board_soc_type(uint32_t board_rev)
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{
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static const char *soc_types[] = {
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NULL, TYPE_BCM2836, TYPE_BCM2837,
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};
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int proc_id = board_processor_id(board_rev);
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if (proc_id >= ARRAY_SIZE(soc_types) || !soc_types[proc_id]) {
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error_report("Unsupported processor id '%d' (board revision: 0x%x)",
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proc_id, board_rev);
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exit(1);
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}
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return soc_types[proc_id];
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}
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static int cores_count(uint32_t board_rev)
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{
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static const int soc_cores_count[] = {
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0, BCM283X_NCPUS, BCM283X_NCPUS,
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};
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int proc_id = board_processor_id(board_rev);
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if (proc_id >= ARRAY_SIZE(soc_cores_count) || !soc_cores_count[proc_id]) {
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error_report("Unsupported processor id '%d' (board revision: 0x%x)",
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proc_id, board_rev);
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exit(1);
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}
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return soc_cores_count[proc_id];
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}
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static const char *board_type(uint32_t board_rev)
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{
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static const char *types[] = {
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"A", "B", "A+", "B+", "2B", "Alpha", "CM1", NULL, "3B", "Zero",
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"CM3", NULL, "Zero W", "3B+", "3A+", NULL, "CM3+", "4B",
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};
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assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */
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int bt = FIELD_EX32(board_rev, REV_CODE, TYPE);
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if (bt >= ARRAY_SIZE(types) || !types[bt]) {
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return "Unknown";
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}
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return types[bt];
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}
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static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info)
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{
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static const uint32_t smpboot[] = {
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0xe1a0e00f, /* mov lr, pc */
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0xe3a0fe00 + (BOARDSETUP_ADDR >> 4), /* mov pc, BOARDSETUP_ADDR */
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0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5;get core ID */
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0xe7e10050, /* ubfx r0, r0, #0, #2 ;extract LSB */
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0xe59f5014, /* ldr r5, =0x400000CC ;load mbox base */
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0xe320f001, /* 1: yield */
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0xe7953200, /* ldr r3, [r5, r0, lsl #4] ;read mbox for our core*/
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0xe3530000, /* cmp r3, #0 ;spin while zero */
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0x0afffffb, /* beq 1b */
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0xe7853200, /* str r3, [r5, r0, lsl #4] ;clear mbox */
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0xe12fff13, /* bx r3 ;jump to target */
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0x400000cc, /* (constant: mailbox 3 read/clear base) */
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};
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/* check that we don't overrun board setup vectors */
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QEMU_BUILD_BUG_ON(SMPBOOT_ADDR + sizeof(smpboot) > MVBAR_ADDR);
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/* check that board setup address is correctly relocated */
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QEMU_BUILD_BUG_ON((BOARDSETUP_ADDR & 0xf) != 0
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|| (BOARDSETUP_ADDR >> 4) >= 0x100);
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rom_add_blob_fixed_as("raspi_smpboot", smpboot, sizeof(smpboot),
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info->smp_loader_start,
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arm_boot_address_space(cpu, info));
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}
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static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info)
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{
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AddressSpace *as = arm_boot_address_space(cpu, info);
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/* Unlike the AArch32 version we don't need to call the board setup hook.
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* The mechanism for doing the spin-table is also entirely different.
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* We must have four 64-bit fields at absolute addresses
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* 0xd8, 0xe0, 0xe8, 0xf0 in RAM, which are the flag variables for
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* our CPUs, and which we must ensure are zero initialized before
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* the primary CPU goes into the kernel. We put these variables inside
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* a rom blob, so that the reset for ROM contents zeroes them for us.
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*/
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static const uint32_t smpboot[] = {
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0xd2801b05, /* mov x5, 0xd8 */
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0xd53800a6, /* mrs x6, mpidr_el1 */
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0x924004c6, /* and x6, x6, #0x3 */
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0xd503205f, /* spin: wfe */
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0xf86678a4, /* ldr x4, [x5,x6,lsl #3] */
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0xb4ffffc4, /* cbz x4, spin */
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0xd2800000, /* mov x0, #0x0 */
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0xd2800001, /* mov x1, #0x0 */
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0xd2800002, /* mov x2, #0x0 */
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0xd2800003, /* mov x3, #0x0 */
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0xd61f0080, /* br x4 */
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};
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static const uint64_t spintables[] = {
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0, 0, 0, 0
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};
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rom_add_blob_fixed_as("raspi_smpboot", smpboot, sizeof(smpboot),
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info->smp_loader_start, as);
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rom_add_blob_fixed_as("raspi_spintables", spintables, sizeof(spintables),
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SPINTABLE_ADDR, as);
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}
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static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info)
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{
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arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR);
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}
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static void reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
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{
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CPUState *cs = CPU(cpu);
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cpu_set_pc(cs, info->smp_loader_start);
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}
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static void setup_boot(MachineState *machine, int version, size_t ram_size)
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{
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static struct arm_boot_info binfo;
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int r;
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binfo.board_id = MACH_TYPE_BCM2708;
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binfo.ram_size = ram_size;
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binfo.nb_cpus = machine->smp.cpus;
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if (version <= 2) {
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/* The rpi1 and 2 require some custom setup code to run in Secure
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* mode before booting a kernel (to set up the SMC vectors so
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* that we get a no-op SMC; this is used by Linux to call the
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* firmware for some cache maintenance operations.
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* The rpi3 doesn't need this.
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*/
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binfo.board_setup_addr = BOARDSETUP_ADDR;
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binfo.write_board_setup = write_board_setup;
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binfo.secure_board_setup = true;
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binfo.secure_boot = true;
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}
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/* Pi2 and Pi3 requires SMP setup */
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if (version >= 2) {
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binfo.smp_loader_start = SMPBOOT_ADDR;
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if (version == 2) {
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binfo.write_secondary_boot = write_smpboot;
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} else {
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binfo.write_secondary_boot = write_smpboot64;
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}
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binfo.secondary_cpu_reset_hook = reset_secondary;
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}
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/* If the user specified a "firmware" image (e.g. UEFI), we bypass
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* the normal Linux boot process
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*/
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if (machine->firmware) {
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hwaddr firmware_addr = version == 3 ? FIRMWARE_ADDR_3 : FIRMWARE_ADDR_2;
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/* load the firmware image (typically kernel.img) */
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r = load_image_targphys(machine->firmware, firmware_addr,
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ram_size - firmware_addr);
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if (r < 0) {
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error_report("Failed to load firmware from %s", machine->firmware);
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exit(1);
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}
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binfo.entry = firmware_addr;
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binfo.firmware_loaded = true;
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}
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arm_load_kernel(ARM_CPU(first_cpu), machine, &binfo);
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}
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static void raspi_machine_init(MachineState *machine)
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{
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RaspiMachineClass *mc = RASPI_MACHINE_GET_CLASS(machine);
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RaspiMachineState *s = RASPI_MACHINE(machine);
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uint32_t board_rev = mc->board_rev;
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int version = board_version(board_rev);
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uint64_t ram_size = board_ram_size(board_rev);
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uint32_t vcram_size;
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DriveInfo *di;
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BlockBackend *blk;
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BusState *bus;
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DeviceState *carddev;
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if (machine->ram_size != ram_size) {
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char *size_str = size_to_str(ram_size);
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error_report("Invalid RAM size, should be %s", size_str);
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g_free(size_str);
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exit(1);
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}
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/* FIXME: Remove when we have custom CPU address space support */
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memory_region_add_subregion_overlap(get_system_memory(), 0,
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machine->ram, 0);
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/* Setup the SOC */
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object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
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board_soc_type(board_rev), &error_abort, NULL);
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object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(machine->ram),
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&error_abort);
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object_property_set_int(OBJECT(&s->soc), board_rev, "board-rev",
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&error_abort);
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object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_abort);
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/* Create and plug in the SD cards */
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di = drive_get_next(IF_SD);
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blk = di ? blk_by_legacy_dinfo(di) : NULL;
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bus = qdev_get_child_bus(DEVICE(&s->soc), "sd-bus");
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if (bus == NULL) {
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error_report("No SD bus found in SOC object");
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exit(1);
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}
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carddev = qdev_create(bus, TYPE_SD_CARD);
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qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
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object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal);
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vcram_size = object_property_get_uint(OBJECT(&s->soc), "vcram-size",
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&error_abort);
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setup_boot(machine, version, machine->ram_size - vcram_size);
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}
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static void raspi_machine_class_init(ObjectClass *oc, void *data)
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{
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MachineClass *mc = MACHINE_CLASS(oc);
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RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
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uint32_t board_rev = (uint32_t)(uintptr_t)data;
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rmc->board_rev = board_rev;
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mc->desc = g_strdup_printf("Raspberry Pi %s", board_type(board_rev));
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mc->init = raspi_machine_init;
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mc->block_default_type = IF_SD;
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mc->no_parallel = 1;
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mc->no_floppy = 1;
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mc->no_cdrom = 1;
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mc->default_cpus = mc->min_cpus = mc->max_cpus = cores_count(board_rev);
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mc->default_ram_size = board_ram_size(board_rev);
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mc->default_ram_id = "ram";
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if (board_version(board_rev) == 2) {
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mc->ignore_memory_transaction_failures = true;
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}
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};
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static const TypeInfo raspi_machine_types[] = {
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{
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.name = MACHINE_TYPE_NAME("raspi2"),
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.parent = TYPE_RASPI_MACHINE,
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.class_init = raspi_machine_class_init,
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.class_data = (void *)0xa21041,
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#ifdef TARGET_AARCH64
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}, {
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.name = MACHINE_TYPE_NAME("raspi3"),
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.parent = TYPE_RASPI_MACHINE,
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.class_init = raspi_machine_class_init,
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.class_data = (void *)0xa02082,
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#endif
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}, {
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.name = TYPE_RASPI_MACHINE,
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.parent = TYPE_MACHINE,
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.instance_size = sizeof(RaspiMachineState),
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.class_size = sizeof(RaspiMachineClass),
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.abstract = true,
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}
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};
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DEFINE_TYPES(raspi_machine_types)
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