mirror of
https://gitlab.com/qemu-project/qemu
synced 2024-09-22 04:01:29 +00:00
ec150c7e09
Back in 2016, we discussed[1] rules for headers, and these were
generally liked:
1. Have a carefully curated header that's included everywhere first. We
got that already thanks to Peter: osdep.h.
2. Headers should normally include everything they need beyond osdep.h.
If exceptions are needed for some reason, they must be documented in
the header. If all that's needed from a header is typedefs, put
those into qemu/typedefs.h instead of including the header.
3. Cyclic inclusion is forbidden.
This patch gets include/ closer to obeying 2.
It's actually extracted from my "[RFC] Baby steps towards saner
headers" series[2], which demonstrates a possible path towards
checking 2 automatically. It passes the RFC test there.
[1] Message-ID: <87h9g8j57d.fsf@blackfin.pond.sub.org>
https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg03345.html
[2] Message-Id: <20190711122827.18970-1-armbru@redhat.com>
https://lists.nongnu.org/archive/html/qemu-devel/2019-07/msg02715.html
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20190812052359.30071-2-armbru@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
55 lines
1.3 KiB
C
55 lines
1.3 KiB
C
#ifndef HW_PCI_HOST_SABRE_H
|
|
#define HW_PCI_HOST_SABRE_H
|
|
|
|
#include "hw/pci/pci.h"
|
|
#include "hw/pci/pci_host.h"
|
|
#include "hw/sparc/sun4u_iommu.h"
|
|
|
|
#define MAX_IVEC 0x40
|
|
|
|
/* OBIO IVEC IRQs */
|
|
#define OBIO_HDD_IRQ 0x20
|
|
#define OBIO_NIC_IRQ 0x21
|
|
#define OBIO_LPT_IRQ 0x22
|
|
#define OBIO_FDD_IRQ 0x27
|
|
#define OBIO_KBD_IRQ 0x29
|
|
#define OBIO_MSE_IRQ 0x2a
|
|
#define OBIO_SER_IRQ 0x2b
|
|
|
|
typedef struct SabrePCIState {
|
|
PCIDevice parent_obj;
|
|
} SabrePCIState;
|
|
|
|
#define TYPE_SABRE_PCI_DEVICE "sabre-pci"
|
|
#define SABRE_PCI_DEVICE(obj) \
|
|
OBJECT_CHECK(SabrePCIState, (obj), TYPE_SABRE_PCI_DEVICE)
|
|
|
|
typedef struct SabreState {
|
|
PCIHostState parent_obj;
|
|
|
|
hwaddr special_base;
|
|
hwaddr mem_base;
|
|
MemoryRegion sabre_config;
|
|
MemoryRegion pci_config;
|
|
MemoryRegion pci_mmio;
|
|
MemoryRegion pci_ioport;
|
|
uint64_t pci_irq_in;
|
|
IOMMUState *iommu;
|
|
PCIBridge *bridgeA;
|
|
PCIBridge *bridgeB;
|
|
uint32_t pci_control[16];
|
|
uint32_t pci_irq_map[8];
|
|
uint32_t pci_err_irq_map[4];
|
|
uint32_t obio_irq_map[32];
|
|
qemu_irq ivec_irqs[MAX_IVEC];
|
|
unsigned int irq_request;
|
|
uint32_t reset_control;
|
|
unsigned int nr_resets;
|
|
} SabreState;
|
|
|
|
#define TYPE_SABRE "sabre"
|
|
#define SABRE_DEVICE(obj) \
|
|
OBJECT_CHECK(SabreState, (obj), TYPE_SABRE)
|
|
|
|
#endif
|