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![]() Features supported : - the 8 STM32L4x5 GPIOs are initialized with their reset values (except IDR, see below) - input mode : setting a pin in input mode "externally" (using input irqs) results in an out irq (transmitted to SYSCFG) - output mode : setting a bit in ODR sets the corresponding out irq (if this line is configured in output mode) - pull-up, pull-down - push-pull, open-drain Difference with the real GPIOs : - Alternate Function and Analog mode aren't implemented : pins in AF/Analog behave like pins in input mode - floating pins stay at their last value - register IDR reset values differ from the real one : values are coherent with the other registers reset values and the fact that AF/Analog modes aren't implemented - setting I/O output speed isn't supported - locking port bits isn't supported - ADC function isn't supported - GPIOH has 16 pins instead of 2 pins - writing to registers LCKR, AFRL, AFRH and ASCR is ineffective Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20240305210444.310665-2-ines.varhol@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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.. | ||
aspeed_gpio.c | ||
bcm2835_gpio.c | ||
bcm2838_gpio.c | ||
gpio_key.c | ||
gpio_pwr.c | ||
imx_gpio.c | ||
Kconfig | ||
max7310.c | ||
meson.build | ||
mpc8xxx.c | ||
npcm7xx_gpio.c | ||
nrf51_gpio.c | ||
omap_gpio.c | ||
pl061.c | ||
sifive_gpio.c | ||
stm32l4x5_gpio.c | ||
trace-events | ||
trace.h | ||
zaurus.c |