Shuuichirou Ishii e31c70ac04 target-arm: Add support for Fujitsu A64FX ... Add a definition for the Fujitsu A64FX processor. The A64FX processor does not implement the AArch32 Execution state, so there are no associated AArch32 Identification registers. For SVE, the A64FX processor supports only 128,256 and 512bit vector lengths. The Identification register values are defined based on the FX700, and have been tested and confirmed. Signed-off-by: Shuuichirou Ishii <ishii.shuuichir@fujitsu.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2021-09-01 11:08:18 +01:00
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alpha
arm	target-arm: Add support for Fujitsu A64FX	2021-09-01 11:08:18 +01:00
avr
cris
hexagon
hppa
i386
m68k
microblaze
mips
nios2
openrisc
ppc	target/ppc: fix vector registers access in gdbstub for little-endian	2021-08-27 12:43:13 +10:00
riscv	target/riscv: Use {get,dest}_gpr for RVV	2021-09-01 11:59:12 +10:00
rx
s390x	arch_init.h: Don't include arch_init.h unnecessarily	2021-08-26 17:02:00 +01:00
sh4
sparc
tricore
xtensa
Kconfig
meson.build