mirror of
https://gitlab.com/qemu-project/qemu
synced 2024-10-07 19:49:59 +00:00
4921a0ce86
This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_gpio model to hw/gpio directory. Note this also removes the trace-events in the hw/riscv directory, since gpio is the only supported trace target in that directory. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1599129623-68957-5-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14 lines
828 B
Meson
14 lines
828 B
Meson
softmmu_ss.add(when: 'CONFIG_E500', if_true: files('mpc8xxx.c'))
|
|
softmmu_ss.add(when: 'CONFIG_GPIO_KEY', if_true: files('gpio_key.c'))
|
|
softmmu_ss.add(when: 'CONFIG_MAX7310', if_true: files('max7310.c'))
|
|
softmmu_ss.add(when: 'CONFIG_PL061', if_true: files('pl061.c'))
|
|
softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_gpio.c'))
|
|
softmmu_ss.add(when: 'CONFIG_ZAURUS', if_true: files('zaurus.c'))
|
|
|
|
softmmu_ss.add(when: 'CONFIG_IMX', if_true: files('imx_gpio.c'))
|
|
softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_gpio.c'))
|
|
softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_gpio.c'))
|
|
softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_gpio.c'))
|
|
softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_gpio.c'))
|
|
softmmu_ss.add(when: 'CONFIG_SIFIVE_GPIO', if_true: files('sifive_gpio.c'))
|