qemu/target
Richard Henderson e116b92d01 qemu-sparc queue
-----BEGIN PGP SIGNATURE-----
 
 iQFSBAABCgA8FiEEzGIauY6CIA2RXMnEW8LFb64PMh8FAmY4wZceHG1hcmsuY2F2
 ZS1heWxhbmRAaWxhbmRlLmNvLnVrAAoJEFvCxW+uDzIftQsH+wfIWymTdQMowfM6
 Ze/T8KODn+MqU5eg25VPSTojnmr7LFaCj2yK6zWX61RwIqtMc3NaxX0G7ksW12/g
 35ACqiEEd5WRDhAtVhj5Wp+WEDoR4AD3LWIaN7a/qjO3qb78l7Bujw3qXzGSq4lQ
 hST6dTgMwn5LhJOyz+5dORVUK1UZSBuDxHeKRHgdoFi6yqGQ5bao5TpaDYOnGSbx
 8KPrAFfXG1T6xRS8Ih5HXAPE5VJztLFPiVtCTTrETDP/o8EzvOZj5y/nJVZXXC3N
 57g+QyJX9EdrRZvobef4LnNnoZyiqG+uQNugglqZqjiiLjl6AzYxI+ed0hU+cZR9
 pz76Hr8=
 =i2cV
 -----END PGP SIGNATURE-----

Merge tag 'qemu-sparc-20240506' of https://github.com/mcayland/qemu into staging

qemu-sparc queue

# -----BEGIN PGP SIGNATURE-----
#
# iQFSBAABCgA8FiEEzGIauY6CIA2RXMnEW8LFb64PMh8FAmY4wZceHG1hcmsuY2F2
# ZS1heWxhbmRAaWxhbmRlLmNvLnVrAAoJEFvCxW+uDzIftQsH+wfIWymTdQMowfM6
# Ze/T8KODn+MqU5eg25VPSTojnmr7LFaCj2yK6zWX61RwIqtMc3NaxX0G7ksW12/g
# 35ACqiEEd5WRDhAtVhj5Wp+WEDoR4AD3LWIaN7a/qjO3qb78l7Bujw3qXzGSq4lQ
# hST6dTgMwn5LhJOyz+5dORVUK1UZSBuDxHeKRHgdoFi6yqGQ5bao5TpaDYOnGSbx
# 8KPrAFfXG1T6xRS8Ih5HXAPE5VJztLFPiVtCTTrETDP/o8EzvOZj5y/nJVZXXC3N
# 57g+QyJX9EdrRZvobef4LnNnoZyiqG+uQNugglqZqjiiLjl6AzYxI+ed0hU+cZR9
# pz76Hr8=
# =i2cV
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 06 May 2024 04:40:07 AM PDT
# gpg:                using RSA key CC621AB98E82200D915CC9C45BC2C56FAE0F321F
# gpg:                issuer "mark.cave-ayland@ilande.co.uk"
# gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" [full]

* tag 'qemu-sparc-20240506' of https://github.com/mcayland/qemu:
  target/sparc: Split out do_ms16b
  target/sparc: Fix FPMERGE
  target/sparc: Fix FMULD8*X16
  target/sparc: Fix FMUL8x16A{U,L}
  target/sparc: Fix FMUL8x16
  target/sparc: Fix FEXPAND
  linux-user/sparc: Add more hwcap bits for sparc64
  hw/sparc64: set iommu_platform=on for virtio devices attached to the sun4u machine
  docs/about: Deprecate the old "UltraSparc" CPU names that contain a "+"
  docs/system/target-sparc: Improve the Sparc documentation
  target/sparc/cpu: Avoid spaces by default in the CPU names
  target/sparc/cpu: Rename the CPU models with a "+" in their names

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-06 10:19:56 -07:00
..
alpha exec/cpu: Extract page-protection definitions to page-protection.h 2024-05-06 11:17:15 +02:00
arm Accelerator patches 2024-05-06 10:19:10 -07:00
avr accel/tcg: Access tcg_cflags with getter / setter 2024-05-06 11:21:05 +02:00
cris exec/cpu: Extract page-protection definitions to page-protection.h 2024-05-06 11:17:15 +02:00
hexagon Accelerator patches 2024-05-06 10:19:10 -07:00
hppa accel/tcg: Access tcg_cflags with getter / setter 2024-05-06 11:21:05 +02:00
i386 Accelerator patches 2024-05-06 10:19:10 -07:00
loongarch accel/tcg: Access tcg_cflags with getter / setter 2024-05-06 11:21:05 +02:00
m68k exec/cpu: Extract page-protection definitions to page-protection.h 2024-05-06 11:17:15 +02:00
microblaze accel/tcg: Access tcg_cflags with getter / setter 2024-05-06 11:21:05 +02:00
mips accel/tcg: Access tcg_cflags with getter / setter 2024-05-06 11:21:05 +02:00
openrisc accel/tcg: Access tcg_cflags with getter / setter 2024-05-06 11:21:05 +02:00
ppc Accelerator patches 2024-05-06 10:19:10 -07:00
riscv accel/tcg: Access tcg_cflags with getter / setter 2024-05-06 11:21:05 +02:00
rx accel/tcg: Access tcg_cflags with getter / setter 2024-05-06 11:21:05 +02:00
s390x exec/cpu: Extract page-protection definitions to page-protection.h 2024-05-06 11:17:15 +02:00
sh4 accel/tcg: Access tcg_cflags with getter / setter 2024-05-06 11:21:05 +02:00
sparc qemu-sparc queue 2024-05-06 10:19:56 -07:00
tricore accel/tcg: Access tcg_cflags with getter / setter 2024-05-06 11:21:05 +02:00
xtensa exec/cpu: Extract page-protection definitions to page-protection.h 2024-05-06 11:17:15 +02:00
Kconfig meson: make target endianneess available to Kconfig 2024-05-03 15:47:47 +02:00
meson.build exec: Expose 'target_page.h' API to user emulation 2024-04-26 15:28:11 +02:00