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https://gitlab.com/qemu-project/qemu
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398 lines
13 KiB
C
398 lines
13 KiB
C
/*
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* ARM Nested Vectored Interrupt Controller
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*
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* Copyright (c) 2006-2007 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licenced under the GPL.
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*
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* The ARMv7M System controller is fairly tightly tied in with the
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* NVIC. Much of that is also implemented here.
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*/
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#include "sysbus.h"
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#include "qemu-timer.h"
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#include "arm-misc.h"
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/* 32 internal lines (16 used for system exceptions) plus 64 external
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interrupt lines. */
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#define GIC_NIRQ 96
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#define NCPU 1
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#define NVIC 1
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/* Only a single "CPU" interface is present. */
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static inline int
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gic_get_current_cpu(void)
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{
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return 0;
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}
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static uint32_t nvic_readl(void *opaque, uint32_t offset);
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static void nvic_writel(void *opaque, uint32_t offset, uint32_t value);
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#include "arm_gic.c"
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typedef struct {
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gic_state gic;
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struct {
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uint32_t control;
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uint32_t reload;
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int64_t tick;
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QEMUTimer *timer;
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} systick;
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} nvic_state;
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/* qemu timers run at 1GHz. We want something closer to 1MHz. */
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#define SYSTICK_SCALE 1000ULL
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#define SYSTICK_ENABLE (1 << 0)
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#define SYSTICK_TICKINT (1 << 1)
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#define SYSTICK_CLKSOURCE (1 << 2)
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#define SYSTICK_COUNTFLAG (1 << 16)
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int system_clock_scale;
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/* Conversion factor from qemu timer to SysTick frequencies. */
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static inline int64_t systick_scale(nvic_state *s)
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{
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if (s->systick.control & SYSTICK_CLKSOURCE)
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return system_clock_scale;
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else
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return 1000;
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}
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static void systick_reload(nvic_state *s, int reset)
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{
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if (reset)
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s->systick.tick = qemu_get_clock_ns(vm_clock);
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s->systick.tick += (s->systick.reload + 1) * systick_scale(s);
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qemu_mod_timer(s->systick.timer, s->systick.tick);
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}
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static void systick_timer_tick(void * opaque)
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{
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nvic_state *s = (nvic_state *)opaque;
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s->systick.control |= SYSTICK_COUNTFLAG;
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if (s->systick.control & SYSTICK_TICKINT) {
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/* Trigger the interrupt. */
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armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
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}
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if (s->systick.reload == 0) {
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s->systick.control &= ~SYSTICK_ENABLE;
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} else {
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systick_reload(s, 0);
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}
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}
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/* The external routines use the hardware vector numbering, ie. the first
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IRQ is #16. The internal GIC routines use #32 as the first IRQ. */
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void armv7m_nvic_set_pending(void *opaque, int irq)
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{
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nvic_state *s = (nvic_state *)opaque;
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if (irq >= 16)
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irq += 16;
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gic_set_pending_private(&s->gic, 0, irq);
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}
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/* Make pending IRQ active. */
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int armv7m_nvic_acknowledge_irq(void *opaque)
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{
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nvic_state *s = (nvic_state *)opaque;
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uint32_t irq;
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irq = gic_acknowledge_irq(&s->gic, 0);
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if (irq == 1023)
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hw_error("Interrupt but no vector\n");
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if (irq >= 32)
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irq -= 16;
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return irq;
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}
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void armv7m_nvic_complete_irq(void *opaque, int irq)
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{
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nvic_state *s = (nvic_state *)opaque;
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if (irq >= 16)
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irq += 16;
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gic_complete_irq(&s->gic, 0, irq);
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}
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static uint32_t nvic_readl(void *opaque, uint32_t offset)
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{
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nvic_state *s = (nvic_state *)opaque;
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uint32_t val;
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int irq;
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switch (offset) {
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case 4: /* Interrupt Control Type. */
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return (GIC_NIRQ / 32) - 1;
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case 0x10: /* SysTick Control and Status. */
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val = s->systick.control;
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s->systick.control &= ~SYSTICK_COUNTFLAG;
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return val;
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case 0x14: /* SysTick Reload Value. */
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return s->systick.reload;
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case 0x18: /* SysTick Current Value. */
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{
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int64_t t;
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if ((s->systick.control & SYSTICK_ENABLE) == 0)
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return 0;
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t = qemu_get_clock_ns(vm_clock);
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if (t >= s->systick.tick)
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return 0;
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val = ((s->systick.tick - (t + 1)) / systick_scale(s)) + 1;
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/* The interrupt in triggered when the timer reaches zero.
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However the counter is not reloaded until the next clock
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tick. This is a hack to return zero during the first tick. */
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if (val > s->systick.reload)
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val = 0;
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return val;
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}
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case 0x1c: /* SysTick Calibration Value. */
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return 10000;
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case 0xd00: /* CPUID Base. */
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return cpu_single_env->cp15.c0_cpuid;
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case 0xd04: /* Interrypt Control State. */
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/* VECTACTIVE */
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val = s->gic.running_irq[0];
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if (val == 1023) {
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val = 0;
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} else if (val >= 32) {
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val -= 16;
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}
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/* RETTOBASE */
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if (s->gic.running_irq[0] == 1023
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|| s->gic.last_active[s->gic.running_irq[0]][0] == 1023) {
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val |= (1 << 11);
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}
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/* VECTPENDING */
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if (s->gic.current_pending[0] != 1023)
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val |= (s->gic.current_pending[0] << 12);
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/* ISRPENDING */
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for (irq = 32; irq < GIC_NIRQ; irq++) {
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if (s->gic.irq_state[irq].pending) {
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val |= (1 << 22);
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break;
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}
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}
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/* PENDSTSET */
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if (s->gic.irq_state[ARMV7M_EXCP_SYSTICK].pending)
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val |= (1 << 26);
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/* PENDSVSET */
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if (s->gic.irq_state[ARMV7M_EXCP_PENDSV].pending)
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val |= (1 << 28);
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/* NMIPENDSET */
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if (s->gic.irq_state[ARMV7M_EXCP_NMI].pending)
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val |= (1 << 31);
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return val;
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case 0xd08: /* Vector Table Offset. */
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return cpu_single_env->v7m.vecbase;
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case 0xd0c: /* Application Interrupt/Reset Control. */
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return 0xfa05000;
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case 0xd10: /* System Control. */
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/* TODO: Implement SLEEPONEXIT. */
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return 0;
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case 0xd14: /* Configuration Control. */
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/* TODO: Implement Configuration Control bits. */
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return 0;
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case 0xd18: case 0xd1c: case 0xd20: /* System Handler Priority. */
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irq = offset - 0xd14;
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val = 0;
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val |= s->gic.priority1[irq++][0];
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val |= s->gic.priority1[irq++][0] << 8;
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val |= s->gic.priority1[irq++][0] << 16;
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val |= s->gic.priority1[irq][0] << 24;
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return val;
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case 0xd24: /* System Handler Status. */
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val = 0;
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if (s->gic.irq_state[ARMV7M_EXCP_MEM].active) val |= (1 << 0);
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if (s->gic.irq_state[ARMV7M_EXCP_BUS].active) val |= (1 << 1);
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if (s->gic.irq_state[ARMV7M_EXCP_USAGE].active) val |= (1 << 3);
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if (s->gic.irq_state[ARMV7M_EXCP_SVC].active) val |= (1 << 7);
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if (s->gic.irq_state[ARMV7M_EXCP_DEBUG].active) val |= (1 << 8);
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if (s->gic.irq_state[ARMV7M_EXCP_PENDSV].active) val |= (1 << 10);
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if (s->gic.irq_state[ARMV7M_EXCP_SYSTICK].active) val |= (1 << 11);
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if (s->gic.irq_state[ARMV7M_EXCP_USAGE].pending) val |= (1 << 12);
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if (s->gic.irq_state[ARMV7M_EXCP_MEM].pending) val |= (1 << 13);
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if (s->gic.irq_state[ARMV7M_EXCP_BUS].pending) val |= (1 << 14);
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if (s->gic.irq_state[ARMV7M_EXCP_SVC].pending) val |= (1 << 15);
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if (s->gic.irq_state[ARMV7M_EXCP_MEM].enabled) val |= (1 << 16);
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if (s->gic.irq_state[ARMV7M_EXCP_BUS].enabled) val |= (1 << 17);
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if (s->gic.irq_state[ARMV7M_EXCP_USAGE].enabled) val |= (1 << 18);
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return val;
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case 0xd28: /* Configurable Fault Status. */
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/* TODO: Implement Fault Status. */
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hw_error("Not implemented: Configurable Fault Status.");
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return 0;
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case 0xd2c: /* Hard Fault Status. */
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case 0xd30: /* Debug Fault Status. */
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case 0xd34: /* Mem Manage Address. */
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case 0xd38: /* Bus Fault Address. */
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case 0xd3c: /* Aux Fault Status. */
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/* TODO: Implement fault status registers. */
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goto bad_reg;
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case 0xd40: /* PFR0. */
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return 0x00000030;
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case 0xd44: /* PRF1. */
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return 0x00000200;
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case 0xd48: /* DFR0. */
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return 0x00100000;
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case 0xd4c: /* AFR0. */
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return 0x00000000;
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case 0xd50: /* MMFR0. */
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return 0x00000030;
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case 0xd54: /* MMFR1. */
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return 0x00000000;
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case 0xd58: /* MMFR2. */
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return 0x00000000;
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case 0xd5c: /* MMFR3. */
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return 0x00000000;
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case 0xd60: /* ISAR0. */
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return 0x01141110;
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case 0xd64: /* ISAR1. */
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return 0x02111000;
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case 0xd68: /* ISAR2. */
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return 0x21112231;
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case 0xd6c: /* ISAR3. */
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return 0x01111110;
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case 0xd70: /* ISAR4. */
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return 0x01310102;
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/* TODO: Implement debug registers. */
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default:
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bad_reg:
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hw_error("NVIC: Bad read offset 0x%x\n", offset);
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}
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}
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static void nvic_writel(void *opaque, uint32_t offset, uint32_t value)
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{
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nvic_state *s = (nvic_state *)opaque;
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uint32_t oldval;
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switch (offset) {
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case 0x10: /* SysTick Control and Status. */
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oldval = s->systick.control;
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s->systick.control &= 0xfffffff8;
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s->systick.control |= value & 7;
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if ((oldval ^ value) & SYSTICK_ENABLE) {
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int64_t now = qemu_get_clock_ns(vm_clock);
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if (value & SYSTICK_ENABLE) {
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if (s->systick.tick) {
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s->systick.tick += now;
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qemu_mod_timer(s->systick.timer, s->systick.tick);
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} else {
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systick_reload(s, 1);
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}
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} else {
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qemu_del_timer(s->systick.timer);
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s->systick.tick -= now;
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if (s->systick.tick < 0)
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s->systick.tick = 0;
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}
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} else if ((oldval ^ value) & SYSTICK_CLKSOURCE) {
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/* This is a hack. Force the timer to be reloaded
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when the reference clock is changed. */
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systick_reload(s, 1);
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}
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break;
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case 0x14: /* SysTick Reload Value. */
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s->systick.reload = value;
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break;
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case 0x18: /* SysTick Current Value. Writes reload the timer. */
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systick_reload(s, 1);
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s->systick.control &= ~SYSTICK_COUNTFLAG;
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break;
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case 0xd04: /* Interrupt Control State. */
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if (value & (1 << 31)) {
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armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI);
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}
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if (value & (1 << 28)) {
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armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV);
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} else if (value & (1 << 27)) {
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s->gic.irq_state[ARMV7M_EXCP_PENDSV].pending = 0;
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gic_update(&s->gic);
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}
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if (value & (1 << 26)) {
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armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
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} else if (value & (1 << 25)) {
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s->gic.irq_state[ARMV7M_EXCP_SYSTICK].pending = 0;
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gic_update(&s->gic);
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}
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break;
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case 0xd08: /* Vector Table Offset. */
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cpu_single_env->v7m.vecbase = value & 0xffffff80;
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break;
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case 0xd0c: /* Application Interrupt/Reset Control. */
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if ((value >> 16) == 0x05fa) {
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if (value & 2) {
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hw_error("VECTCLRACTIVE not implemented");
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}
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if (value & 5) {
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hw_error("System reset");
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}
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}
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break;
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case 0xd10: /* System Control. */
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case 0xd14: /* Configuration Control. */
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/* TODO: Implement control registers. */
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goto bad_reg;
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case 0xd18: case 0xd1c: case 0xd20: /* System Handler Priority. */
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{
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int irq;
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irq = offset - 0xd14;
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s->gic.priority1[irq++][0] = value & 0xff;
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s->gic.priority1[irq++][0] = (value >> 8) & 0xff;
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s->gic.priority1[irq++][0] = (value >> 16) & 0xff;
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s->gic.priority1[irq][0] = (value >> 24) & 0xff;
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gic_update(&s->gic);
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}
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break;
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case 0xd24: /* System Handler Control. */
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/* TODO: Real hardware allows you to set/clear the active bits
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under some circumstances. We don't implement this. */
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s->gic.irq_state[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;
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s->gic.irq_state[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
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s->gic.irq_state[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0;
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break;
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case 0xd28: /* Configurable Fault Status. */
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case 0xd2c: /* Hard Fault Status. */
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case 0xd30: /* Debug Fault Status. */
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case 0xd34: /* Mem Manage Address. */
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case 0xd38: /* Bus Fault Address. */
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case 0xd3c: /* Aux Fault Status. */
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goto bad_reg;
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default:
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bad_reg:
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hw_error("NVIC: Bad write offset 0x%x\n", offset);
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}
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}
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static const VMStateDescription vmstate_nvic = {
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.name = "armv7m_nvic",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(systick.control, nvic_state),
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VMSTATE_UINT32(systick.reload, nvic_state),
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VMSTATE_INT64(systick.tick, nvic_state),
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VMSTATE_TIMER(systick.timer, nvic_state),
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VMSTATE_END_OF_LIST()
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}
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};
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static int armv7m_nvic_init(SysBusDevice *dev)
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{
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nvic_state *s= FROM_SYSBUSGIC(nvic_state, dev);
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gic_init(&s->gic);
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cpu_register_physical_memory(0xe000e000, 0x1000, s->gic.iomemtype);
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s->systick.timer = qemu_new_timer_ns(vm_clock, systick_timer_tick, s);
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vmstate_register(&dev->qdev, -1, &vmstate_nvic, s);
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return 0;
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}
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static void armv7m_nvic_register_devices(void)
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{
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sysbus_register_dev("armv7m_nvic", sizeof(nvic_state), armv7m_nvic_init);
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}
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device_init(armv7m_nvic_register_devices)
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