mirror of
https://gitlab.com/qemu-project/qemu
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daf866b606
This patch removes the insn32-64.decode decode file and consolidates the instructions into the general RISC-V insn32.decode decode tree. This means that all of the instructions are avaliable in both the 32-bit and 64-bit builds. This also means that we run a check to ensure we are running a 64-bit softmmu before we execute the 64-bit only instructions. This allows us to include the 32-bit instructions in the 64-bit build, while also ensuring that 32-bit only software can not execute the instructions. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: db709360e2be47d2f9c6483ab973fe4791aefa77.1619234854.git.alistair.francis@wdc.com
37 lines
1,023 B
Meson
37 lines
1,023 B
Meson
# FIXME extra_args should accept files()
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dir = meson.current_source_dir()
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gen32 = [
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decodetree.process('insn16.decode', extra_args: [dir / 'insn16-32.decode', '--static-decode=decode_insn16', '--insnwidth=16']),
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decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
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]
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gen64 = [
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decodetree.process('insn16.decode', extra_args: [dir / 'insn16-64.decode', '--static-decode=decode_insn16', '--insnwidth=16']),
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decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
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]
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riscv_ss = ss.source_set()
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riscv_ss.add(when: 'TARGET_RISCV32', if_true: gen32)
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riscv_ss.add(when: 'TARGET_RISCV64', if_true: gen64)
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riscv_ss.add(files(
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'cpu.c',
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'cpu_helper.c',
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'csr.c',
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'fpu_helper.c',
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'gdbstub.c',
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'op_helper.c',
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'vector_helper.c',
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'translate.c',
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))
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riscv_softmmu_ss = ss.source_set()
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riscv_softmmu_ss.add(files(
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'arch_dump.c',
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'pmp.c',
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'monitor.c',
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'machine.c'
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))
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target_arch += {'riscv': riscv_ss}
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target_softmmu_arch += {'riscv': riscv_softmmu_ss}
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