qemu/hw
Laszlo Ersek dab30fbef3 acpi: cpuhp: fix guest-visible maximum access size to the legacy reg block
The modern ACPI CPU hotplug interface was introduced in the following
series (aa1dd39ca307..679dd1a957df), released in v2.7.0:

  1  abd49bc2ed docs: update ACPI CPU hotplug spec with new protocol
  2  16bcab97eb pc: piix4/ich9: add 'cpu-hotplug-legacy' property
  3  5e1b5d9388 acpi: cpuhp: add CPU devices AML with _STA method
  4  ac35f13ba8 pc: acpi: introduce AcpiDeviceIfClass.madt_cpu hook
  5  d2238cb678 acpi: cpuhp: implement hot-add parts of CPU hotplug
                  interface
  6  8872c25a26 acpi: cpuhp: implement hot-remove parts of CPU hotplug
                  interface
  7  76623d00ae acpi: cpuhp: add cpu._OST handling
  8  679dd1a957 pc: use new CPU hotplug interface since 2.7 machine type

Before patch#1, "docs/specs/acpi_cpu_hotplug.txt" only specified 1-byte
accesses for the hotplug register block.  Patch#1 preserved the same
restriction for the legacy register block, but:

- it specified DWORD accesses for some of the modern registers,

- in particular, the switch from the legacy block to the modern block
  would require a DWORD write to the *legacy* block.

The latter functionality was then implemented in cpu_status_write()
[hw/acpi/cpu_hotplug.c], in patch#8.

Unfortunately, all DWORD accesses depended on a dormant bug: the one
introduced in earlier commit a014ed07bd ("memory: accept mismatching
sizes in memory_region_access_valid", 2013-05-29); first released in
v1.6.0.  Due to commit a014ed07bd, the DWORD accesses to the *legacy*
CPU hotplug register block would work in spite of the above series *not*
relaxing "valid.max_access_size = 1" in "hw/acpi/cpu_hotplug.c":

> static const MemoryRegionOps AcpiCpuHotplug_ops = {
>     .read = cpu_status_read,
>     .write = cpu_status_write,
>     .endianness = DEVICE_LITTLE_ENDIAN,
>     .valid = {
>         .min_access_size = 1,
>         .max_access_size = 1,
>     },
> };

Later, in commits e6d0c3ce68 ("acpi: cpuhp: introduce 'Command data 2'
field", 2020-01-22) and ae340aa3d2 ("acpi: cpuhp: spec: add typical
usecases", 2020-01-22), first released in v5.0.0, the modern CPU hotplug
interface (including the documentation) was extended with another DWORD
*read* access, namely to the "Command data 2" register, which would be
important for the guest to confirm whether it managed to switch the
register block from legacy to modern.

This functionality too silently depended on the bug from commit
a014ed07bd.

In commit 5d971f9e67 ('memory: Revert "memory: accept mismatching sizes
in memory_region_access_valid"', 2020-06-26), first released in v5.1.0,
the bug from commit a014ed07bd was fixed (the commit was reverted).
That swiftly exposed the bug in "AcpiCpuHotplug_ops", still present from
the v2.7.0 series quoted at the top -- namely the fact that
"valid.max_access_size = 1" didn't match what the guest was supposed to
do, according to the spec ("docs/specs/acpi_cpu_hotplug.txt").

The symptom is that the "modern interface negotiation protocol"
described in commit ae340aa3d2:

> +      Use following steps to detect and enable modern CPU hotplug interface:
> +        1. Store 0x0 to the 'CPU selector' register,
> +           attempting to switch to modern mode
> +        2. Store 0x0 to the 'CPU selector' register,
> +           to ensure valid selector value
> +        3. Store 0x0 to the 'Command field' register,
> +        4. Read the 'Command data 2' register.
> +           If read value is 0x0, the modern interface is enabled.
> +           Otherwise legacy or no CPU hotplug interface available

falls apart for the guest: steps 1 and 2 are lost, because they are DWORD
writes; so no switching happens.  Step 3 (a single-byte write) is not
lost, but it has no effect; see the condition in cpu_status_write() in
patch#8.  And step 4 *misleads* the guest into thinking that the switch
worked: the DWORD read is lost again -- it returns zero to the guest
without ever reaching the device model, so the guest never learns the
switch didn't work.

This means that guest behavior centered on the "Command data 2" register
worked *only* in the v5.0.0 release; it got effectively regressed in
v5.1.0.

To make things *even more* complicated, the breakage was (and remains, as
of today) visible with TCG acceleration only.  Commit 5d971f9e67 makes
no difference with KVM acceleration -- the DWORD accesses still work,
despite "valid.max_access_size = 1".

As commit 5d971f9e67 suggests, fix the problem by raising
"valid.max_access_size" to 4 -- the spec now clearly instructs the guest
to perform DWORD accesses to the legacy register block too, for enabling
(and verifying!) the modern block.  In order to keep compatibility for the
device model implementation though, set "impl.max_access_size = 1", so
that wide accesses be split before they reach the legacy read/write
handlers, like they always have been on KVM, and like they were on TCG
before 5d971f9e67 (v5.1.0).

Tested with:

- OVMF IA32 + qemu-system-i386, CPU hotplug/hot-unplug with SMM,
  intermixed with ACPI S3 suspend/resume, using KVM accel
  (regression-test);

- OVMF IA32X64 + qemu-system-x86_64, CPU hotplug/hot-unplug with SMM,
  intermixed with ACPI S3 suspend/resume, using KVM accel
  (regression-test);

- OVMF IA32 + qemu-system-i386, SMM enabled, using TCG accel; verified the
  register block switch and the present/possible CPU counting through the
  modern hotplug interface, during OVMF boot (bugfix test);

- I do not have any testcase (guest payload) for regression-testing CPU
  hotplug through the *legacy* CPU hotplug register block.

Cc: "Michael S. Tsirkin" <mst@redhat.com>
Cc: Ani Sinha <ani@anisinha.ca>
Cc: Ard Biesheuvel <ardb@kernel.org>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Philippe Mathieu-Daudé <philmd@linaro.org>
Cc: qemu-stable@nongnu.org
Ref: "IO port write width clamping differs between TCG and KVM"
Link: http://mid.mail-archive.com/aaedee84-d3ed-a4f9-21e7-d221a28d1683@redhat.com
Link: https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg00199.html
Reported-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20230105161804.82486-1-lersek@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-01-08 01:54:23 -05:00
..
9pfs hw/9pfs: Replace the direct call to xxxat() APIs with a wrapper 2022-12-23 11:48:13 +01:00
acpi acpi: cpuhp: fix guest-visible maximum access size to the legacy reg block 2023-01-08 01:54:23 -05:00
adc hw/adc: Make adci[*] R/W in NPCM7XX ADC 2022-07-18 13:20:14 +01:00
alpha include/hw/pci: Break inclusion loop pci_bridge.h and cxl.h 2023-01-08 01:54:22 -05:00
arm i.MX7D: Connect IRQs to GPIO devices. 2023-01-05 15:04:17 +00:00
audio include/hw/pci: Split pci_device.h off pci.h 2023-01-08 01:54:22 -05:00
avr
block hw/virtio: generalise CHR_EVENT_CLOSED handling 2022-12-01 02:30:13 -05:00
char include/hw/pci: Split pci_device.h off pci.h 2023-01-08 01:54:22 -05:00
core hw/acpi/aml-build: Only generate cluster node in PPTT when specified 2023-01-08 01:54:23 -05:00
cpu
cris
cxl hw/cxl/cdat: CXL CDAT Data Object Exchange implementation 2022-11-07 13:12:19 -05:00
display include/hw/pci: Split pci_device.h off pci.h 2023-01-08 01:54:22 -05:00
dma treewide: Remove the unnecessary space before semicolon 2022-10-24 13:41:10 +02:00
gpio hw/gpio/meson: Introduce dedicated config switch for hw/gpio/mpc8xxx 2022-10-17 16:15:09 -03:00
hppa hw: Remove unused MAX_IDE_BUS define 2022-10-31 11:32:07 +01:00
hyperv hw/hyperv/vmbus: Use device_cold_reset() and bus_cold_reset() 2022-12-16 15:55:32 +00:00
i2c hw/acpi/Kconfig: Rename ACPI_X86_ICH to ACPI_ICH9 2023-01-08 01:54:21 -05:00
i386 include/hw/pci: Split pci_device.h off pci.h 2023-01-08 01:54:22 -05:00
ide include/hw/pci: Split pci_device.h off pci.h 2023-01-08 01:54:22 -05:00
input hw/input/tsc2xxx: Constify set_transform()'s MouseTransformInfo arg 2023-01-05 14:11:15 +00:00
intc pull-loongarch-20230106 2023-01-07 14:25:38 +00:00
ipack include/hw/pci: Split pci_device.h off pci.h 2023-01-08 01:54:22 -05:00
ipmi include/hw/pci: Split pci_device.h off pci.h 2023-01-08 01:54:22 -05:00
isa include/hw/pci: Split pci_device.h off pci.h 2023-01-08 01:54:22 -05:00
loongarch hw/intc/loongarch_pch: Change default irq number of pch irq controller 2023-01-06 14:12:43 +08:00
m68k hw: Add compat machines for 8.0 2022-12-21 06:35:28 -05:00
mem hw/cxl/device: Add Flex Bus Port DVSEC 2022-12-21 07:32:24 -05:00
microblaze hw/microblaze: pass random seed to fdt 2022-09-21 19:59:56 +02:00
mips include/hw/pci: Split pci_device.h off pci.h 2023-01-08 01:54:22 -05:00
misc include/hw/pci: Split pci_device.h off pci.h 2023-01-08 01:54:22 -05:00
net include/hw/pci: Split pci_device.h off pci.h 2023-01-08 01:54:22 -05:00
nios2 hw/nios2: set machine->fdt in nios2_load_dtb() 2022-10-17 16:15:10 -03:00
nubus
nvme include/hw/pci: Split pci_device.h off pci.h 2023-01-08 01:54:22 -05:00
nvram qapi machine: Elide redundant has_FOO in generated C 2022-12-14 20:04:47 +01:00
openrisc openrisc: re-randomize rng-seed on reboot 2022-10-27 11:34:31 +01:00
pci include/hw/pci: Split pci_device.h off pci.h 2023-01-08 01:54:22 -05:00
pci-bridge include/hw/cxl: Move typedef PXBDev to cxl.h, and put it to use 2023-01-08 01:54:22 -05:00
pci-host include/hw/pci: Split pci_device.h off pci.h 2023-01-08 01:54:22 -05:00
pcmcia
ppc include/hw/pci: Split pci_device.h off pci.h 2023-01-08 01:54:22 -05:00
rdma include/hw/pci: Split pci_device.h off pci.h 2023-01-08 01:54:22 -05:00
remote Replace use of qdev_reset_all() with device_cold_reset() 2022-12-16 15:55:32 +00:00
riscv hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization 2023-01-06 10:42:55 +10:00
rtc goldfish_rtc: Add big-endian property 2022-09-04 07:02:56 +01:00
rx rx: re-randomize rng-seed on reboot 2022-10-27 11:34:31 +01:00
s390x include/hw/pci: Split pci_device.h off pci.h 2023-01-08 01:54:22 -05:00
scsi include/hw/pci: Split pci_device.h off pci.h 2023-01-08 01:54:22 -05:00
sd hw/sd/sdhci: Support big endian SD host controller interfaces 2022-12-21 14:17:55 -03:00
sensor hw/sensor: Add Renesas ISL69259 device model 2022-07-14 16:24:38 +02:00
sh4
smbios include/hw/pci: Split pci_device.h off pci.h 2023-01-08 01:54:22 -05:00
sparc
sparc64 hw: Remove unused MAX_IDE_BUS define 2022-10-31 11:32:07 +01:00
ssi aspeed/smc: Cache AspeedSMCClass 2022-10-24 11:20:15 +02:00
timer i.MX6UL: Add a specific GPT timer instance for the i.MX6UL 2023-01-05 15:02:08 +00:00
tpm tpm_crb: Avoid backend startup just before shutdown under Xen 2022-09-09 17:55:59 -04:00
tricore
usb include/hw/pci: Split pci_device.h off pci.h 2023-01-08 01:54:22 -05:00
vfio include/hw/pci: Split pci_device.h off pci.h 2023-01-08 01:54:22 -05:00
virtio virtio-pci: fix proxy->vector_irqfd leak in virtio_pci_set_guest_notifiers 2023-01-08 01:54:23 -05:00
watchdog include/hw/pci: Split pci_device.h off pci.h 2023-01-08 01:54:22 -05:00
xen include/hw/pci: Break inclusion loop pci_bridge.h and cxl.h 2023-01-08 01:54:22 -05:00
xenpv
xtensa
Kconfig hw/loongarch: Add support loongson3 virt machine type. 2022-06-06 18:09:03 +00:00
meson.build hw/loongarch: Add support loongson3 virt machine type. 2022-06-06 18:09:03 +00:00