mirror of
https://gitlab.com/qemu-project/qemu
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d64e5eabc4
Add code needed to get a functional PCI subsytem when using in conjunction with upstream Linux guest (4.13+). Tested to work against "e1000e" (network adapter, using MSI interrupts) as well as "usb-ehci" (USB controller, using legacy PCI interrupts). Based on "i.MX6 Applications Processor Reference Manual" (Document Number: IMX6DQRM Rev. 4) as well as corresponding dirver in Linux kernel (circa 4.13 - 4.16 found in drivers/pci/dwc/*) Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
103 lines
2.6 KiB
C
103 lines
2.6 KiB
C
/*
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* Copyright (c) 2017, Impinj, Inc.
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*
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* Designware PCIe IP block emulation
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/>.
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*/
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#ifndef DESIGNWARE_H
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#define DESIGNWARE_H
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#include "hw/hw.h"
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#include "hw/sysbus.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_bus.h"
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#include "hw/pci/pcie_host.h"
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#include "hw/pci/pci_bridge.h"
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#define TYPE_DESIGNWARE_PCIE_HOST "designware-pcie-host"
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#define DESIGNWARE_PCIE_HOST(obj) \
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OBJECT_CHECK(DesignwarePCIEHost, (obj), TYPE_DESIGNWARE_PCIE_HOST)
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#define TYPE_DESIGNWARE_PCIE_ROOT "designware-pcie-root"
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#define DESIGNWARE_PCIE_ROOT(obj) \
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OBJECT_CHECK(DesignwarePCIERoot, (obj), TYPE_DESIGNWARE_PCIE_ROOT)
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struct DesignwarePCIERoot;
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typedef struct DesignwarePCIERoot DesignwarePCIERoot;
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typedef struct DesignwarePCIEViewport {
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DesignwarePCIERoot *root;
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MemoryRegion cfg;
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MemoryRegion mem;
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uint64_t base;
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uint64_t target;
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uint32_t limit;
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uint32_t cr[2];
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bool inbound;
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} DesignwarePCIEViewport;
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typedef struct DesignwarePCIEMSIBank {
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uint32_t enable;
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uint32_t mask;
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uint32_t status;
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} DesignwarePCIEMSIBank;
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typedef struct DesignwarePCIEMSI {
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uint64_t base;
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MemoryRegion iomem;
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#define DESIGNWARE_PCIE_NUM_MSI_BANKS 1
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DesignwarePCIEMSIBank intr[DESIGNWARE_PCIE_NUM_MSI_BANKS];
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} DesignwarePCIEMSI;
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struct DesignwarePCIERoot {
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PCIBridge parent_obj;
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uint32_t atu_viewport;
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#define DESIGNWARE_PCIE_VIEWPORT_OUTBOUND 0
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#define DESIGNWARE_PCIE_VIEWPORT_INBOUND 1
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#define DESIGNWARE_PCIE_NUM_VIEWPORTS 4
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DesignwarePCIEViewport viewports[2][DESIGNWARE_PCIE_NUM_VIEWPORTS];
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DesignwarePCIEMSI msi;
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};
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typedef struct DesignwarePCIEHost {
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PCIHostState parent_obj;
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DesignwarePCIERoot root;
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struct {
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AddressSpace address_space;
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MemoryRegion address_space_root;
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MemoryRegion memory;
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MemoryRegion io;
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qemu_irq irqs[4];
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} pci;
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MemoryRegion mmio;
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} DesignwarePCIEHost;
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#endif /* DESIGNWARE_H */
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