Richard Henderson c1ddc18f37 tcg/s390x: Fix encoding of VRIc, VRSa, VRSc insns ... While the format names the second vector register 'v3', it is still in the second position (bits 12-15) and the argument to RXB must match. Example error: - e7 00 00 10 2a 33 verllf %v16,%v0,16 + e7 00 00 10 2c 33 verllf %v16,%v16,16 Cc: qemu-stable@nongnu.org Reported-by: Michael Tokarev <mjt@tls.msk.ru> Fixes: 22cb37b417 ("tcg/s390x: Implement vector shift operations") Fixes: 79cada8693 ("tcg/s390x: Implement tcg_out_dup*_vec") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2054 Reviewed-by: Thomas Huth <thuth@redhat.com> Tested-by: Michael Tokarev <mjt@tls.msk.ru> Message-Id: <20240117213646.159697-2-richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>		2024-01-23 13:22:46 +10:00
..
tcg-target-con-set.h	tcg/{i386, s390x}: Add earlyclobber to the op_add2's first output	2023-07-23 17:58:19 +01:00
tcg-target-con-str.h	tcg/s390x: Simplify constraints on qemu_ld/st	2023-05-11 09:53:41 +01:00
tcg-target-reg-bits.h	tcg: Split out tcg-target-reg-bits.h	2023-06-05 12:04:28 -07:00
tcg-target.c.inc	tcg/s390x: Fix encoding of VRIc, VRSa, VRSc insns	2024-01-23 13:22:46 +10:00
tcg-target.h	tcg: Remove TCG_TARGET_HAS_neg_{i32,i64}	2023-11-06 08:27:21 -08:00
tcg-target.opc.h	tcg/s390x: Implement TCG_TARGET_HAS_sat_vec	2021-10-05 16:53:17 -07:00