mirror of
https://gitlab.com/qemu-project/qemu
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333 lines
8.8 KiB
C
333 lines
8.8 KiB
C
/*
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* SuperH Timer modules.
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*
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* Copyright (c) 2007 Magnus Damm
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* Based on arm_timer.c by Paul Brook
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* Copyright (c) 2005-2006 CodeSourcery.
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*
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* This code is licensed under the GPL.
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*/
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#include "hw/hw.h"
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#include "hw/sh4/sh.h"
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#include "qemu/timer.h"
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#include "exec/address-spaces.h"
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#include "hw/ptimer.h"
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//#define DEBUG_TIMER
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#define TIMER_TCR_TPSC (7 << 0)
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#define TIMER_TCR_CKEG (3 << 3)
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#define TIMER_TCR_UNIE (1 << 5)
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#define TIMER_TCR_ICPE (3 << 6)
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#define TIMER_TCR_UNF (1 << 8)
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#define TIMER_TCR_ICPF (1 << 9)
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#define TIMER_TCR_RESERVED (0x3f << 10)
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#define TIMER_FEAT_CAPT (1 << 0)
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#define TIMER_FEAT_EXTCLK (1 << 1)
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#define OFFSET_TCOR 0
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#define OFFSET_TCNT 1
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#define OFFSET_TCR 2
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#define OFFSET_TCPR 3
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typedef struct {
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ptimer_state *timer;
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uint32_t tcnt;
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uint32_t tcor;
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uint32_t tcr;
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uint32_t tcpr;
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int freq;
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int int_level;
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int old_level;
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int feat;
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int enabled;
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qemu_irq irq;
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} sh_timer_state;
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/* Check all active timers, and schedule the next timer interrupt. */
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static void sh_timer_update(sh_timer_state *s)
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{
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int new_level = s->int_level && (s->tcr & TIMER_TCR_UNIE);
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if (new_level != s->old_level)
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qemu_set_irq (s->irq, new_level);
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s->old_level = s->int_level;
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s->int_level = new_level;
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}
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static uint32_t sh_timer_read(void *opaque, hwaddr offset)
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{
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sh_timer_state *s = (sh_timer_state *)opaque;
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switch (offset >> 2) {
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case OFFSET_TCOR:
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return s->tcor;
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case OFFSET_TCNT:
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return ptimer_get_count(s->timer);
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case OFFSET_TCR:
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return s->tcr | (s->int_level ? TIMER_TCR_UNF : 0);
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case OFFSET_TCPR:
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if (s->feat & TIMER_FEAT_CAPT)
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return s->tcpr;
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default:
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hw_error("sh_timer_read: Bad offset %x\n", (int)offset);
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return 0;
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}
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}
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static void sh_timer_write(void *opaque, hwaddr offset,
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uint32_t value)
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{
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sh_timer_state *s = (sh_timer_state *)opaque;
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int freq;
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switch (offset >> 2) {
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case OFFSET_TCOR:
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s->tcor = value;
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ptimer_set_limit(s->timer, s->tcor, 0);
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break;
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case OFFSET_TCNT:
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s->tcnt = value;
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ptimer_set_count(s->timer, s->tcnt);
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break;
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case OFFSET_TCR:
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if (s->enabled) {
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/* Pause the timer if it is running. This may cause some
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inaccuracy dure to rounding, but avoids a whole lot of other
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messyness. */
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ptimer_stop(s->timer);
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}
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freq = s->freq;
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/* ??? Need to recalculate expiry time after changing divisor. */
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switch (value & TIMER_TCR_TPSC) {
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case 0: freq >>= 2; break;
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case 1: freq >>= 4; break;
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case 2: freq >>= 6; break;
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case 3: freq >>= 8; break;
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case 4: freq >>= 10; break;
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case 6:
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case 7: if (s->feat & TIMER_FEAT_EXTCLK) break;
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default: hw_error("sh_timer_write: Reserved TPSC value\n"); break;
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}
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switch ((value & TIMER_TCR_CKEG) >> 3) {
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case 0: break;
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case 1:
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case 2:
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case 3: if (s->feat & TIMER_FEAT_EXTCLK) break;
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default: hw_error("sh_timer_write: Reserved CKEG value\n"); break;
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}
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switch ((value & TIMER_TCR_ICPE) >> 6) {
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case 0: break;
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case 2:
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case 3: if (s->feat & TIMER_FEAT_CAPT) break;
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default: hw_error("sh_timer_write: Reserved ICPE value\n"); break;
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}
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if ((value & TIMER_TCR_UNF) == 0)
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s->int_level = 0;
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value &= ~TIMER_TCR_UNF;
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if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT)))
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hw_error("sh_timer_write: Reserved ICPF value\n");
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value &= ~TIMER_TCR_ICPF; /* capture not supported */
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if (value & TIMER_TCR_RESERVED)
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hw_error("sh_timer_write: Reserved TCR bits set\n");
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s->tcr = value;
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ptimer_set_limit(s->timer, s->tcor, 0);
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ptimer_set_freq(s->timer, freq);
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if (s->enabled) {
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/* Restart the timer if still enabled. */
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ptimer_run(s->timer, 0);
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}
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break;
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case OFFSET_TCPR:
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if (s->feat & TIMER_FEAT_CAPT) {
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s->tcpr = value;
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break;
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}
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default:
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hw_error("sh_timer_write: Bad offset %x\n", (int)offset);
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}
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sh_timer_update(s);
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}
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static void sh_timer_start_stop(void *opaque, int enable)
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{
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sh_timer_state *s = (sh_timer_state *)opaque;
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#ifdef DEBUG_TIMER
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printf("sh_timer_start_stop %d (%d)\n", enable, s->enabled);
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#endif
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if (s->enabled && !enable) {
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ptimer_stop(s->timer);
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}
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if (!s->enabled && enable) {
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ptimer_run(s->timer, 0);
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}
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s->enabled = !!enable;
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#ifdef DEBUG_TIMER
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printf("sh_timer_start_stop done %d\n", s->enabled);
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#endif
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}
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static void sh_timer_tick(void *opaque)
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{
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sh_timer_state *s = (sh_timer_state *)opaque;
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s->int_level = s->enabled;
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sh_timer_update(s);
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}
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static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq)
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{
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sh_timer_state *s;
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QEMUBH *bh;
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s = (sh_timer_state *)g_malloc0(sizeof(sh_timer_state));
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s->freq = freq;
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s->feat = feat;
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s->tcor = 0xffffffff;
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s->tcnt = 0xffffffff;
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s->tcpr = 0xdeadbeef;
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s->tcr = 0;
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s->enabled = 0;
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s->irq = irq;
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bh = qemu_bh_new(sh_timer_tick, s);
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s->timer = ptimer_init(bh);
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sh_timer_write(s, OFFSET_TCOR >> 2, s->tcor);
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sh_timer_write(s, OFFSET_TCNT >> 2, s->tcnt);
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sh_timer_write(s, OFFSET_TCPR >> 2, s->tcpr);
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sh_timer_write(s, OFFSET_TCR >> 2, s->tcpr);
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/* ??? Save/restore. */
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return s;
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}
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typedef struct {
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MemoryRegion iomem;
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MemoryRegion iomem_p4;
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MemoryRegion iomem_a7;
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void *timer[3];
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int level[3];
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uint32_t tocr;
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uint32_t tstr;
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int feat;
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} tmu012_state;
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static uint64_t tmu012_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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tmu012_state *s = (tmu012_state *)opaque;
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#ifdef DEBUG_TIMER
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printf("tmu012_read 0x%lx\n", (unsigned long) offset);
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#endif
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if (offset >= 0x20) {
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if (!(s->feat & TMU012_FEAT_3CHAN))
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hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
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return sh_timer_read(s->timer[2], offset - 0x20);
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}
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if (offset >= 0x14)
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return sh_timer_read(s->timer[1], offset - 0x14);
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if (offset >= 0x08)
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return sh_timer_read(s->timer[0], offset - 0x08);
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if (offset == 4)
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return s->tstr;
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if ((s->feat & TMU012_FEAT_TOCR) && offset == 0)
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return s->tocr;
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hw_error("tmu012_write: Bad offset %x\n", (int)offset);
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return 0;
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}
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static void tmu012_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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tmu012_state *s = (tmu012_state *)opaque;
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#ifdef DEBUG_TIMER
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printf("tmu012_write 0x%lx 0x%08x\n", (unsigned long) offset, value);
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#endif
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if (offset >= 0x20) {
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if (!(s->feat & TMU012_FEAT_3CHAN))
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hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
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sh_timer_write(s->timer[2], offset - 0x20, value);
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return;
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}
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if (offset >= 0x14) {
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sh_timer_write(s->timer[1], offset - 0x14, value);
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return;
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}
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if (offset >= 0x08) {
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sh_timer_write(s->timer[0], offset - 0x08, value);
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return;
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}
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if (offset == 4) {
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sh_timer_start_stop(s->timer[0], value & (1 << 0));
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sh_timer_start_stop(s->timer[1], value & (1 << 1));
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if (s->feat & TMU012_FEAT_3CHAN)
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sh_timer_start_stop(s->timer[2], value & (1 << 2));
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else
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if (value & (1 << 2))
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hw_error("tmu012_write: Bad channel\n");
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s->tstr = value;
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return;
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}
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if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) {
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s->tocr = value & (1 << 0);
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}
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}
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static const MemoryRegionOps tmu012_ops = {
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.read = tmu012_read,
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.write = tmu012_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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void tmu012_init(MemoryRegion *sysmem, hwaddr base,
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int feat, uint32_t freq,
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qemu_irq ch0_irq, qemu_irq ch1_irq,
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qemu_irq ch2_irq0, qemu_irq ch2_irq1)
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{
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tmu012_state *s;
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int timer_feat = (feat & TMU012_FEAT_EXTCLK) ? TIMER_FEAT_EXTCLK : 0;
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s = (tmu012_state *)g_malloc0(sizeof(tmu012_state));
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s->feat = feat;
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s->timer[0] = sh_timer_init(freq, timer_feat, ch0_irq);
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s->timer[1] = sh_timer_init(freq, timer_feat, ch1_irq);
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if (feat & TMU012_FEAT_3CHAN)
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s->timer[2] = sh_timer_init(freq, timer_feat | TIMER_FEAT_CAPT,
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ch2_irq0); /* ch2_irq1 not supported */
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memory_region_init_io(&s->iomem, &tmu012_ops, s,
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"timer", 0x100000000ULL);
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memory_region_init_alias(&s->iomem_p4, "timer-p4",
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&s->iomem, 0, 0x1000);
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memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4);
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memory_region_init_alias(&s->iomem_a7, "timer-a7",
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&s->iomem, 0, 0x1000);
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memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7);
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/* ??? Save/restore. */
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}
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