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https://gitlab.com/qemu-project/qemu
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159 lines
6.5 KiB
C
159 lines
6.5 KiB
C
/*
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* linux/include/video/vga.h -- standard VGA chipset interaction
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*
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* Copyright 1999 Jeff Garzik <jgarzik@pobox.com>
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*
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* Copyright history from vga16fb.c:
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* Copyright 1999 Ben Pfaff and Petr Vandrovec
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* Based on VGA info at http://www.osdever.net/FreeVGA/home.htm
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* Based on VESA framebuffer (c) 1998 Gerd Knorr
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*
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*/
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#ifndef __linux_video_vga_h__
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#define __linux_video_vga_h__
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/* Some of the code below is taken from SVGAlib. The original,
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unmodified copyright notice for that code is below. */
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/* VGAlib version 1.2 - (c) 1993 Tommy Frandsen */
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/* */
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/* This library is free software; you can redistribute it and/or */
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/* modify it without any restrictions. This library is distributed */
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/* in the hope that it will be useful, but without any warranty. */
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/* Multi-chipset support Copyright 1993 Harm Hanemaayer */
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/* partially copyrighted (C) 1993 by Hartmut Schirmer */
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/* VGA data register ports */
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#define VGA_CRT_DC 0x3D5 /* CRT Controller Data Register - color emulation */
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#define VGA_CRT_DM 0x3B5 /* CRT Controller Data Register - mono emulation */
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#define VGA_ATT_R 0x3C1 /* Attribute Controller Data Read Register */
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#define VGA_ATT_W 0x3C0 /* Attribute Controller Data Write Register */
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#define VGA_GFX_D 0x3CF /* Graphics Controller Data Register */
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#define VGA_SEQ_D 0x3C5 /* Sequencer Data Register */
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#define VGA_MIS_R 0x3CC /* Misc Output Read Register */
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#define VGA_MIS_W 0x3C2 /* Misc Output Write Register */
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#define VGA_FTC_R 0x3CA /* Feature Control Read Register */
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#define VGA_IS1_RC 0x3DA /* Input Status Register 1 - color emulation */
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#define VGA_IS1_RM 0x3BA /* Input Status Register 1 - mono emulation */
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#define VGA_PEL_D 0x3C9 /* PEL Data Register */
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#define VGA_PEL_MSK 0x3C6 /* PEL mask register */
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/* EGA-specific registers */
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#define EGA_GFX_E0 0x3CC /* Graphics enable processor 0 */
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#define EGA_GFX_E1 0x3CA /* Graphics enable processor 1 */
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/* VGA index register ports */
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#define VGA_CRT_IC 0x3D4 /* CRT Controller Index - color emulation */
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#define VGA_CRT_IM 0x3B4 /* CRT Controller Index - mono emulation */
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#define VGA_ATT_IW 0x3C0 /* Attribute Controller Index & Data Write Register */
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#define VGA_GFX_I 0x3CE /* Graphics Controller Index */
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#define VGA_SEQ_I 0x3C4 /* Sequencer Index */
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#define VGA_PEL_IW 0x3C8 /* PEL Write Index */
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#define VGA_PEL_IR 0x3C7 /* PEL Read Index */
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/* standard VGA indexes max counts */
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#define VGA_CRT_C 0x19 /* Number of CRT Controller Registers */
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#define VGA_ATT_C 0x15 /* Number of Attribute Controller Registers */
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#define VGA_GFX_C 0x09 /* Number of Graphics Controller Registers */
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#define VGA_SEQ_C 0x05 /* Number of Sequencer Registers */
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#define VGA_MIS_C 0x01 /* Number of Misc Output Register */
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/* VGA misc register bit masks */
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#define VGA_MIS_COLOR 0x01
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#define VGA_MIS_ENB_MEM_ACCESS 0x02
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#define VGA_MIS_DCLK_28322_720 0x04
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#define VGA_MIS_ENB_PLL_LOAD (0x04 | 0x08)
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#define VGA_MIS_SEL_HIGH_PAGE 0x20
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/* VGA CRT controller register indices */
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#define VGA_CRTC_H_TOTAL 0
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#define VGA_CRTC_H_DISP 1
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#define VGA_CRTC_H_BLANK_START 2
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#define VGA_CRTC_H_BLANK_END 3
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#define VGA_CRTC_H_SYNC_START 4
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#define VGA_CRTC_H_SYNC_END 5
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#define VGA_CRTC_V_TOTAL 6
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#define VGA_CRTC_OVERFLOW 7
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#define VGA_CRTC_PRESET_ROW 8
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#define VGA_CRTC_MAX_SCAN 9
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#define VGA_CRTC_CURSOR_START 0x0A
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#define VGA_CRTC_CURSOR_END 0x0B
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#define VGA_CRTC_START_HI 0x0C
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#define VGA_CRTC_START_LO 0x0D
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#define VGA_CRTC_CURSOR_HI 0x0E
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#define VGA_CRTC_CURSOR_LO 0x0F
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#define VGA_CRTC_V_SYNC_START 0x10
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#define VGA_CRTC_V_SYNC_END 0x11
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#define VGA_CRTC_V_DISP_END 0x12
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#define VGA_CRTC_OFFSET 0x13
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#define VGA_CRTC_UNDERLINE 0x14
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#define VGA_CRTC_V_BLANK_START 0x15
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#define VGA_CRTC_V_BLANK_END 0x16
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#define VGA_CRTC_MODE 0x17
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#define VGA_CRTC_LINE_COMPARE 0x18
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#define VGA_CRTC_REGS VGA_CRT_C
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/* VGA CRT controller bit masks */
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#define VGA_CR11_LOCK_CR0_CR7 0x80 /* lock writes to CR0 - CR7 */
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#define VGA_CR17_H_V_SIGNALS_ENABLED 0x80
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/* VGA attribute controller register indices */
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#define VGA_ATC_PALETTE0 0x00
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#define VGA_ATC_PALETTE1 0x01
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#define VGA_ATC_PALETTE2 0x02
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#define VGA_ATC_PALETTE3 0x03
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#define VGA_ATC_PALETTE4 0x04
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#define VGA_ATC_PALETTE5 0x05
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#define VGA_ATC_PALETTE6 0x06
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#define VGA_ATC_PALETTE7 0x07
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#define VGA_ATC_PALETTE8 0x08
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#define VGA_ATC_PALETTE9 0x09
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#define VGA_ATC_PALETTEA 0x0A
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#define VGA_ATC_PALETTEB 0x0B
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#define VGA_ATC_PALETTEC 0x0C
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#define VGA_ATC_PALETTED 0x0D
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#define VGA_ATC_PALETTEE 0x0E
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#define VGA_ATC_PALETTEF 0x0F
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#define VGA_ATC_MODE 0x10
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#define VGA_ATC_OVERSCAN 0x11
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#define VGA_ATC_PLANE_ENABLE 0x12
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#define VGA_ATC_PEL 0x13
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#define VGA_ATC_COLOR_PAGE 0x14
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#define VGA_AR_ENABLE_DISPLAY 0x20
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/* VGA sequencer register indices */
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#define VGA_SEQ_RESET 0x00
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#define VGA_SEQ_CLOCK_MODE 0x01
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#define VGA_SEQ_PLANE_WRITE 0x02
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#define VGA_SEQ_CHARACTER_MAP 0x03
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#define VGA_SEQ_MEMORY_MODE 0x04
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/* VGA sequencer register bit masks */
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#define VGA_SR01_CHAR_CLK_8DOTS 0x01 /* bit 0: character clocks 8 dots wide are generated */
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#define VGA_SR01_SCREEN_OFF 0x20 /* bit 5: Screen is off */
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#define VGA_SR02_ALL_PLANES 0x0F /* bits 3-0: enable access to all planes */
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#define VGA_SR04_EXT_MEM 0x02 /* bit 1: allows complete mem access to 256K */
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#define VGA_SR04_SEQ_MODE 0x04 /* bit 2: directs system to use a sequential addressing mode */
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#define VGA_SR04_CHN_4M 0x08 /* bit 3: selects modulo 4 addressing for CPU access to display memory */
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/* VGA graphics controller register indices */
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#define VGA_GFX_SR_VALUE 0x00
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#define VGA_GFX_SR_ENABLE 0x01
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#define VGA_GFX_COMPARE_VALUE 0x02
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#define VGA_GFX_DATA_ROTATE 0x03
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#define VGA_GFX_PLANE_READ 0x04
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#define VGA_GFX_MODE 0x05
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#define VGA_GFX_MISC 0x06
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#define VGA_GFX_COMPARE_MASK 0x07
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#define VGA_GFX_BIT_MASK 0x08
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/* VGA graphics controller bit masks */
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#define VGA_GR06_GRAPHICS_MODE 0x01
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#endif /* __linux_video_vga_h__ */
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