qemu/hw/char
Peter Maydell f00f57f344 This PR includes multiple fixes and features for RISC-V:
- Fixes a bug in printing trap causes
  - Allows 16-bit writes to the SiFive test device. This fixes the
    failure to reboot the RISC-V virt machine
  - Support for the Microchip PolarFire SoC and Icicle Kit
  - A reafactor of RISC-V code out of hw/riscv
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Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200910' into staging

This PR includes multiple fixes and features for RISC-V:
 - Fixes a bug in printing trap causes
 - Allows 16-bit writes to the SiFive test device. This fixes the
   failure to reboot the RISC-V virt machine
 - Support for the Microchip PolarFire SoC and Icicle Kit
 - A reafactor of RISC-V code out of hw/riscv

# gpg: Signature made Thu 10 Sep 2020 19:08:06 BST
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20200910: (30 commits)
  hw/riscv: Sort the Kconfig options in alphabetical order
  hw/riscv: Drop CONFIG_SIFIVE
  hw/riscv: Always build riscv_hart.c
  hw/riscv: Move sifive_test model to hw/misc
  hw/riscv: Move sifive_uart model to hw/char
  hw/riscv: Move riscv_htif model to hw/char
  hw/riscv: Move sifive_plic model to hw/intc
  hw/riscv: Move sifive_clint model to hw/intc
  hw/riscv: Move sifive_gpio model to hw/gpio
  hw/riscv: Move sifive_u_otp model to hw/misc
  hw/riscv: Move sifive_u_prci model to hw/misc
  hw/riscv: Move sifive_e_prci model to hw/misc
  hw/riscv: sifive_u: Connect a DMA controller
  hw/riscv: clint: Avoid using hard-coded timebase frequency
  hw/riscv: microchip_pfsoc: Hook GPIO controllers
  hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs
  hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23
  hw/net: cadence_gem: Add a new 'phy-addr' property
  hw/riscv: microchip_pfsoc: Connect a DMA controller
  hw/dma: Add SiFive platform DMA controller emulation
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

# Conflicts:
#	hw/riscv/trace-events
2020-09-13 20:29:35 +01:00
..
avr_usart.c hw/char: avr: Add limited support for USART peripheral 2020-07-11 11:02:05 +02:00
bcm2835_aux.c qdev: set properties with device_class_set_props() 2020-01-24 20:59:15 +01:00
cadence_uart.c hw/char/cadence_uart: add clock support 2020-04-30 15:35:41 +01:00
cmsdk-apb-uart.c qdev: set properties with device_class_set_props() 2020-01-24 20:59:15 +01:00
debugcon.c Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
digic-uart.c qdev: set properties with device_class_set_props() 2020-01-24 20:59:15 +01:00
escc.c qdev: set properties with device_class_set_props() 2020-01-24 20:59:15 +01:00
etraxfs_ser.c Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
exynos4210_uart.c Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
grlib_apbuart.c Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
ibex_uart.c hw/char: Convert the Ibex UART to use the registerfields API 2020-07-13 17:25:37 -07:00
imx_serial.c qdev: set properties with device_class_set_props() 2020-01-24 20:59:15 +01:00
ipoctal232.c Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
Kconfig hw/riscv: Move sifive_uart model to hw/char 2020-09-09 15:54:19 -07:00
lm32_juart.c Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
lm32_uart.c Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
mcf_uart.c Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
mchp_pfsoc_mmuart.c hw/char: Add Microchip PolarFire SoC MMUART emulation 2020-09-09 15:54:18 -07:00
meson.build hw/riscv: Move sifive_uart model to hw/char 2020-09-09 15:54:19 -07:00
milkymist-uart.c Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
nrf51_uart.c qdev: set properties with device_class_set_props() 2020-01-24 20:59:15 +01:00
omap_uart.c serial: start making SerialMM a sysbus device 2020-01-07 17:23:30 +04:00
parallel-isa.c isa: Convert uses of isa_create() with Coccinelle 2020-06-15 22:05:28 +02:00
parallel.c Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
pl011.c qdev: set properties with device_class_set_props() 2020-01-24 20:59:15 +01:00
renesas_sci.c hw/char: RX62N serial communication interface (SCI) 2020-06-22 18:37:12 +02:00
riscv_htif.c hw/riscv: Move riscv_htif model to hw/char 2020-09-09 15:54:19 -07:00
sclpconsole-lm.c Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
sclpconsole.c Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
serial-isa.c Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
serial-pci-multi.c error: Eliminate error_propagate() with Coccinelle, part 1 2020-07-10 15:18:08 +02:00
serial-pci.c Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
serial.c error: Eliminate error_propagate() with Coccinelle, part 1 2020-07-10 15:18:08 +02:00
sh_serial.c chardev: Use QEMUChrEvent enum in IOEventHandler typedef 2020-01-08 11:15:35 +01:00
sifive_uart.c hw/riscv: Move sifive_uart model to hw/char 2020-09-09 15:54:19 -07:00
spapr_vty.c Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
stm32f2xx_usart.c qdev: set properties with device_class_set_props() 2020-01-24 20:59:15 +01:00
terminal3270.c Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
trace-events trace-events: Fix attribution of trace points to source 2020-09-09 17:17:58 +01:00
trace.h trace: switch position of headers to what Meson requires 2020-08-21 06:18:24 -04:00
virtio-console.c Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
virtio-serial-bus.c virtio-serial-bus: Move QOM macros to header 2020-08-27 14:04:54 -04:00
xen_console.c Include sysemu/sysemu.h a lot less 2019-08-16 13:31:53 +02:00
xilinx_uartlite.c Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00