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https://gitlab.com/qemu-project/qemu
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649 lines
18 KiB
C
649 lines
18 KiB
C
/*
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* TI OMAP interrupt controller emulation.
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*
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* Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
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* Copyright (C) 2007-2008 Nokia Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hw/hw.h"
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#include "hw/arm/omap.h"
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#include "hw/sysbus.h"
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/* Interrupt Handlers */
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struct omap_intr_handler_bank_s {
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uint32_t irqs;
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uint32_t inputs;
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uint32_t mask;
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uint32_t fiq;
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uint32_t sens_edge;
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uint32_t swi;
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unsigned char priority[32];
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};
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struct omap_intr_handler_s {
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SysBusDevice busdev;
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qemu_irq *pins;
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qemu_irq parent_intr[2];
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MemoryRegion mmio;
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void *iclk;
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void *fclk;
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unsigned char nbanks;
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int level_only;
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uint32_t size;
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uint8_t revision;
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/* state */
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uint32_t new_agr[2];
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int sir_intr[2];
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int autoidle;
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uint32_t mask;
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struct omap_intr_handler_bank_s bank[3];
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};
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static void omap_inth_sir_update(struct omap_intr_handler_s *s, int is_fiq)
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{
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int i, j, sir_intr, p_intr, p, f;
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uint32_t level;
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sir_intr = 0;
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p_intr = 255;
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/* Find the interrupt line with the highest dynamic priority.
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* Note: 0 denotes the hightest priority.
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* If all interrupts have the same priority, the default order is IRQ_N,
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* IRQ_N-1,...,IRQ_0. */
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for (j = 0; j < s->nbanks; ++j) {
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level = s->bank[j].irqs & ~s->bank[j].mask &
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(is_fiq ? s->bank[j].fiq : ~s->bank[j].fiq);
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for (f = ffs(level), i = f - 1, level >>= f - 1; f; i += f,
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level >>= f) {
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p = s->bank[j].priority[i];
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if (p <= p_intr) {
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p_intr = p;
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sir_intr = 32 * j + i;
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}
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f = ffs(level >> 1);
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}
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}
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s->sir_intr[is_fiq] = sir_intr;
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}
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static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq)
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{
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int i;
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uint32_t has_intr = 0;
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for (i = 0; i < s->nbanks; ++i)
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has_intr |= s->bank[i].irqs & ~s->bank[i].mask &
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(is_fiq ? s->bank[i].fiq : ~s->bank[i].fiq);
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if (s->new_agr[is_fiq] & has_intr & s->mask) {
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s->new_agr[is_fiq] = 0;
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omap_inth_sir_update(s, is_fiq);
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qemu_set_irq(s->parent_intr[is_fiq], 1);
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}
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}
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#define INT_FALLING_EDGE 0
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#define INT_LOW_LEVEL 1
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static void omap_set_intr(void *opaque, int irq, int req)
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{
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struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque;
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uint32_t rise;
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struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
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int n = irq & 31;
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if (req) {
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rise = ~bank->irqs & (1 << n);
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if (~bank->sens_edge & (1 << n))
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rise &= ~bank->inputs;
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bank->inputs |= (1 << n);
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if (rise) {
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bank->irqs |= rise;
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omap_inth_update(ih, 0);
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omap_inth_update(ih, 1);
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}
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} else {
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rise = bank->sens_edge & bank->irqs & (1 << n);
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bank->irqs &= ~rise;
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bank->inputs &= ~(1 << n);
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}
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}
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/* Simplified version with no edge detection */
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static void omap_set_intr_noedge(void *opaque, int irq, int req)
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{
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struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque;
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uint32_t rise;
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struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
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int n = irq & 31;
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if (req) {
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rise = ~bank->inputs & (1 << n);
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if (rise) {
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bank->irqs |= bank->inputs |= rise;
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omap_inth_update(ih, 0);
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omap_inth_update(ih, 1);
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}
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} else
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bank->irqs = (bank->inputs &= ~(1 << n)) | bank->swi;
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}
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static uint64_t omap_inth_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
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int i, offset = addr;
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int bank_no = offset >> 8;
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int line_no;
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struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
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offset &= 0xff;
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switch (offset) {
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case 0x00: /* ITR */
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return bank->irqs;
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case 0x04: /* MIR */
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return bank->mask;
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case 0x10: /* SIR_IRQ_CODE */
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case 0x14: /* SIR_FIQ_CODE */
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if (bank_no != 0)
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break;
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line_no = s->sir_intr[(offset - 0x10) >> 2];
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bank = &s->bank[line_no >> 5];
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i = line_no & 31;
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if (((bank->sens_edge >> i) & 1) == INT_FALLING_EDGE)
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bank->irqs &= ~(1 << i);
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return line_no;
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case 0x18: /* CONTROL_REG */
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if (bank_no != 0)
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break;
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return 0;
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case 0x1c: /* ILR0 */
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case 0x20: /* ILR1 */
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case 0x24: /* ILR2 */
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case 0x28: /* ILR3 */
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case 0x2c: /* ILR4 */
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case 0x30: /* ILR5 */
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case 0x34: /* ILR6 */
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case 0x38: /* ILR7 */
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case 0x3c: /* ILR8 */
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case 0x40: /* ILR9 */
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case 0x44: /* ILR10 */
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case 0x48: /* ILR11 */
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case 0x4c: /* ILR12 */
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case 0x50: /* ILR13 */
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case 0x54: /* ILR14 */
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case 0x58: /* ILR15 */
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case 0x5c: /* ILR16 */
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case 0x60: /* ILR17 */
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case 0x64: /* ILR18 */
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case 0x68: /* ILR19 */
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case 0x6c: /* ILR20 */
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case 0x70: /* ILR21 */
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case 0x74: /* ILR22 */
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case 0x78: /* ILR23 */
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case 0x7c: /* ILR24 */
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case 0x80: /* ILR25 */
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case 0x84: /* ILR26 */
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case 0x88: /* ILR27 */
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case 0x8c: /* ILR28 */
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case 0x90: /* ILR29 */
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case 0x94: /* ILR30 */
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case 0x98: /* ILR31 */
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i = (offset - 0x1c) >> 2;
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return (bank->priority[i] << 2) |
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(((bank->sens_edge >> i) & 1) << 1) |
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((bank->fiq >> i) & 1);
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case 0x9c: /* ISR */
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return 0x00000000;
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}
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OMAP_BAD_REG(addr);
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return 0;
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}
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static void omap_inth_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
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int i, offset = addr;
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int bank_no = offset >> 8;
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struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
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offset &= 0xff;
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switch (offset) {
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case 0x00: /* ITR */
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/* Important: ignore the clearing if the IRQ is level-triggered and
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the input bit is 1 */
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bank->irqs &= value | (bank->inputs & bank->sens_edge);
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return;
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case 0x04: /* MIR */
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bank->mask = value;
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omap_inth_update(s, 0);
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omap_inth_update(s, 1);
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return;
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case 0x10: /* SIR_IRQ_CODE */
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case 0x14: /* SIR_FIQ_CODE */
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OMAP_RO_REG(addr);
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break;
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case 0x18: /* CONTROL_REG */
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if (bank_no != 0)
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break;
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if (value & 2) {
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qemu_set_irq(s->parent_intr[1], 0);
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s->new_agr[1] = ~0;
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omap_inth_update(s, 1);
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}
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if (value & 1) {
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qemu_set_irq(s->parent_intr[0], 0);
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s->new_agr[0] = ~0;
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omap_inth_update(s, 0);
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}
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return;
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case 0x1c: /* ILR0 */
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case 0x20: /* ILR1 */
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case 0x24: /* ILR2 */
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case 0x28: /* ILR3 */
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case 0x2c: /* ILR4 */
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case 0x30: /* ILR5 */
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case 0x34: /* ILR6 */
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case 0x38: /* ILR7 */
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case 0x3c: /* ILR8 */
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case 0x40: /* ILR9 */
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case 0x44: /* ILR10 */
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case 0x48: /* ILR11 */
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case 0x4c: /* ILR12 */
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case 0x50: /* ILR13 */
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case 0x54: /* ILR14 */
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case 0x58: /* ILR15 */
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case 0x5c: /* ILR16 */
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case 0x60: /* ILR17 */
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case 0x64: /* ILR18 */
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case 0x68: /* ILR19 */
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case 0x6c: /* ILR20 */
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case 0x70: /* ILR21 */
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case 0x74: /* ILR22 */
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case 0x78: /* ILR23 */
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case 0x7c: /* ILR24 */
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case 0x80: /* ILR25 */
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case 0x84: /* ILR26 */
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case 0x88: /* ILR27 */
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case 0x8c: /* ILR28 */
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case 0x90: /* ILR29 */
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case 0x94: /* ILR30 */
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case 0x98: /* ILR31 */
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i = (offset - 0x1c) >> 2;
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bank->priority[i] = (value >> 2) & 0x1f;
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bank->sens_edge &= ~(1 << i);
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bank->sens_edge |= ((value >> 1) & 1) << i;
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bank->fiq &= ~(1 << i);
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bank->fiq |= (value & 1) << i;
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return;
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case 0x9c: /* ISR */
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for (i = 0; i < 32; i ++)
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if (value & (1 << i)) {
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omap_set_intr(s, 32 * bank_no + i, 1);
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return;
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}
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return;
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}
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OMAP_BAD_REG(addr);
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}
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static const MemoryRegionOps omap_inth_mem_ops = {
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.read = omap_inth_read,
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.write = omap_inth_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static void omap_inth_reset(DeviceState *dev)
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{
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struct omap_intr_handler_s *s = FROM_SYSBUS(struct omap_intr_handler_s,
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SYS_BUS_DEVICE(dev));
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int i;
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for (i = 0; i < s->nbanks; ++i){
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s->bank[i].irqs = 0x00000000;
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s->bank[i].mask = 0xffffffff;
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s->bank[i].sens_edge = 0x00000000;
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s->bank[i].fiq = 0x00000000;
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s->bank[i].inputs = 0x00000000;
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s->bank[i].swi = 0x00000000;
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memset(s->bank[i].priority, 0, sizeof(s->bank[i].priority));
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if (s->level_only)
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s->bank[i].sens_edge = 0xffffffff;
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}
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s->new_agr[0] = ~0;
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s->new_agr[1] = ~0;
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s->sir_intr[0] = 0;
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s->sir_intr[1] = 0;
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s->autoidle = 0;
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s->mask = ~0;
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qemu_set_irq(s->parent_intr[0], 0);
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qemu_set_irq(s->parent_intr[1], 0);
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}
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static int omap_intc_init(SysBusDevice *dev)
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{
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struct omap_intr_handler_s *s;
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s = FROM_SYSBUS(struct omap_intr_handler_s, dev);
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if (!s->iclk) {
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hw_error("omap-intc: clk not connected\n");
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}
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s->nbanks = 1;
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sysbus_init_irq(dev, &s->parent_intr[0]);
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sysbus_init_irq(dev, &s->parent_intr[1]);
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qdev_init_gpio_in(&dev->qdev, omap_set_intr, s->nbanks * 32);
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memory_region_init_io(&s->mmio, &omap_inth_mem_ops, s,
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"omap-intc", s->size);
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sysbus_init_mmio(dev, &s->mmio);
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return 0;
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}
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static Property omap_intc_properties[] = {
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DEFINE_PROP_UINT32("size", struct omap_intr_handler_s, size, 0x100),
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DEFINE_PROP_PTR("clk", struct omap_intr_handler_s, iclk),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void omap_intc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
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k->init = omap_intc_init;
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dc->reset = omap_inth_reset;
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dc->props = omap_intc_properties;
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}
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static const TypeInfo omap_intc_info = {
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.name = "omap-intc",
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(struct omap_intr_handler_s),
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.class_init = omap_intc_class_init,
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};
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static uint64_t omap2_inth_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
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int offset = addr;
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int bank_no, line_no;
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struct omap_intr_handler_bank_s *bank = NULL;
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if ((offset & 0xf80) == 0x80) {
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bank_no = (offset & 0x60) >> 5;
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if (bank_no < s->nbanks) {
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offset &= ~0x60;
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bank = &s->bank[bank_no];
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} else {
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OMAP_BAD_REG(addr);
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return 0;
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}
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}
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switch (offset) {
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case 0x00: /* INTC_REVISION */
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return s->revision;
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case 0x10: /* INTC_SYSCONFIG */
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return (s->autoidle >> 2) & 1;
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case 0x14: /* INTC_SYSSTATUS */
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return 1; /* RESETDONE */
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case 0x40: /* INTC_SIR_IRQ */
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return s->sir_intr[0];
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case 0x44: /* INTC_SIR_FIQ */
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return s->sir_intr[1];
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case 0x48: /* INTC_CONTROL */
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return (!s->mask) << 2; /* GLOBALMASK */
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case 0x4c: /* INTC_PROTECTION */
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return 0;
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case 0x50: /* INTC_IDLE */
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return s->autoidle & 3;
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/* Per-bank registers */
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case 0x80: /* INTC_ITR */
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return bank->inputs;
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case 0x84: /* INTC_MIR */
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return bank->mask;
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case 0x88: /* INTC_MIR_CLEAR */
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case 0x8c: /* INTC_MIR_SET */
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return 0;
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case 0x90: /* INTC_ISR_SET */
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return bank->swi;
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case 0x94: /* INTC_ISR_CLEAR */
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return 0;
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case 0x98: /* INTC_PENDING_IRQ */
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return bank->irqs & ~bank->mask & ~bank->fiq;
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case 0x9c: /* INTC_PENDING_FIQ */
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return bank->irqs & ~bank->mask & bank->fiq;
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/* Per-line registers */
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case 0x100 ... 0x300: /* INTC_ILR */
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bank_no = (offset - 0x100) >> 7;
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if (bank_no > s->nbanks)
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break;
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bank = &s->bank[bank_no];
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line_no = (offset & 0x7f) >> 2;
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return (bank->priority[line_no] << 2) |
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((bank->fiq >> line_no) & 1);
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}
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OMAP_BAD_REG(addr);
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return 0;
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}
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static void omap2_inth_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
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int offset = addr;
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int bank_no, line_no;
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struct omap_intr_handler_bank_s *bank = NULL;
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if ((offset & 0xf80) == 0x80) {
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bank_no = (offset & 0x60) >> 5;
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if (bank_no < s->nbanks) {
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offset &= ~0x60;
|
|
bank = &s->bank[bank_no];
|
|
} else {
|
|
OMAP_BAD_REG(addr);
|
|
return;
|
|
}
|
|
}
|
|
|
|
switch (offset) {
|
|
case 0x10: /* INTC_SYSCONFIG */
|
|
s->autoidle &= 4;
|
|
s->autoidle |= (value & 1) << 2;
|
|
if (value & 2) /* SOFTRESET */
|
|
omap_inth_reset(&s->busdev.qdev);
|
|
return;
|
|
|
|
case 0x48: /* INTC_CONTROL */
|
|
s->mask = (value & 4) ? 0 : ~0; /* GLOBALMASK */
|
|
if (value & 2) { /* NEWFIQAGR */
|
|
qemu_set_irq(s->parent_intr[1], 0);
|
|
s->new_agr[1] = ~0;
|
|
omap_inth_update(s, 1);
|
|
}
|
|
if (value & 1) { /* NEWIRQAGR */
|
|
qemu_set_irq(s->parent_intr[0], 0);
|
|
s->new_agr[0] = ~0;
|
|
omap_inth_update(s, 0);
|
|
}
|
|
return;
|
|
|
|
case 0x4c: /* INTC_PROTECTION */
|
|
/* TODO: Make a bitmap (or sizeof(char)map) of access privileges
|
|
* for every register, see Chapter 3 and 4 for privileged mode. */
|
|
if (value & 1)
|
|
fprintf(stderr, "%s: protection mode enable attempt\n",
|
|
__FUNCTION__);
|
|
return;
|
|
|
|
case 0x50: /* INTC_IDLE */
|
|
s->autoidle &= ~3;
|
|
s->autoidle |= value & 3;
|
|
return;
|
|
|
|
/* Per-bank registers */
|
|
case 0x84: /* INTC_MIR */
|
|
bank->mask = value;
|
|
omap_inth_update(s, 0);
|
|
omap_inth_update(s, 1);
|
|
return;
|
|
|
|
case 0x88: /* INTC_MIR_CLEAR */
|
|
bank->mask &= ~value;
|
|
omap_inth_update(s, 0);
|
|
omap_inth_update(s, 1);
|
|
return;
|
|
|
|
case 0x8c: /* INTC_MIR_SET */
|
|
bank->mask |= value;
|
|
return;
|
|
|
|
case 0x90: /* INTC_ISR_SET */
|
|
bank->irqs |= bank->swi |= value;
|
|
omap_inth_update(s, 0);
|
|
omap_inth_update(s, 1);
|
|
return;
|
|
|
|
case 0x94: /* INTC_ISR_CLEAR */
|
|
bank->swi &= ~value;
|
|
bank->irqs = bank->swi & bank->inputs;
|
|
return;
|
|
|
|
/* Per-line registers */
|
|
case 0x100 ... 0x300: /* INTC_ILR */
|
|
bank_no = (offset - 0x100) >> 7;
|
|
if (bank_no > s->nbanks)
|
|
break;
|
|
bank = &s->bank[bank_no];
|
|
line_no = (offset & 0x7f) >> 2;
|
|
bank->priority[line_no] = (value >> 2) & 0x3f;
|
|
bank->fiq &= ~(1 << line_no);
|
|
bank->fiq |= (value & 1) << line_no;
|
|
return;
|
|
|
|
case 0x00: /* INTC_REVISION */
|
|
case 0x14: /* INTC_SYSSTATUS */
|
|
case 0x40: /* INTC_SIR_IRQ */
|
|
case 0x44: /* INTC_SIR_FIQ */
|
|
case 0x80: /* INTC_ITR */
|
|
case 0x98: /* INTC_PENDING_IRQ */
|
|
case 0x9c: /* INTC_PENDING_FIQ */
|
|
OMAP_RO_REG(addr);
|
|
return;
|
|
}
|
|
OMAP_BAD_REG(addr);
|
|
}
|
|
|
|
static const MemoryRegionOps omap2_inth_mem_ops = {
|
|
.read = omap2_inth_read,
|
|
.write = omap2_inth_write,
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
.valid = {
|
|
.min_access_size = 4,
|
|
.max_access_size = 4,
|
|
},
|
|
};
|
|
|
|
static int omap2_intc_init(SysBusDevice *dev)
|
|
{
|
|
struct omap_intr_handler_s *s;
|
|
s = FROM_SYSBUS(struct omap_intr_handler_s, dev);
|
|
if (!s->iclk) {
|
|
hw_error("omap2-intc: iclk not connected\n");
|
|
}
|
|
if (!s->fclk) {
|
|
hw_error("omap2-intc: fclk not connected\n");
|
|
}
|
|
s->level_only = 1;
|
|
s->nbanks = 3;
|
|
sysbus_init_irq(dev, &s->parent_intr[0]);
|
|
sysbus_init_irq(dev, &s->parent_intr[1]);
|
|
qdev_init_gpio_in(&dev->qdev, omap_set_intr_noedge, s->nbanks * 32);
|
|
memory_region_init_io(&s->mmio, &omap2_inth_mem_ops, s,
|
|
"omap2-intc", 0x1000);
|
|
sysbus_init_mmio(dev, &s->mmio);
|
|
return 0;
|
|
}
|
|
|
|
static Property omap2_intc_properties[] = {
|
|
DEFINE_PROP_UINT8("revision", struct omap_intr_handler_s,
|
|
revision, 0x21),
|
|
DEFINE_PROP_PTR("iclk", struct omap_intr_handler_s, iclk),
|
|
DEFINE_PROP_PTR("fclk", struct omap_intr_handler_s, fclk),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void omap2_intc_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
|
|
|
|
k->init = omap2_intc_init;
|
|
dc->reset = omap_inth_reset;
|
|
dc->props = omap2_intc_properties;
|
|
}
|
|
|
|
static const TypeInfo omap2_intc_info = {
|
|
.name = "omap2-intc",
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(struct omap_intr_handler_s),
|
|
.class_init = omap2_intc_class_init,
|
|
};
|
|
|
|
static void omap_intc_register_types(void)
|
|
{
|
|
type_register_static(&omap_intc_info);
|
|
type_register_static(&omap2_intc_info);
|
|
}
|
|
|
|
type_init(omap_intc_register_types)
|