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qemu/target-tricore
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Bastian Koppelmann c433a17141 target-tricore: Move general CHECK_REG_PAIR of decode_rrr_divide 
The add.f and sub.f to be implemented don't use 64 bit registers
and a general usage of CHECK_REG_PAIR would always generate an
exception for them.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <1457708597-3025-3-git-send-email-kbastian@mail.uni-paderborn.de>
2016-03-23 09:22:48 +01:00
..
cpu-qom.h target-tricore: Remove the dummy interrupt boilerplate 2014-09-25 18:54:22 +01:00
cpu.c tricore: Clean up includes 2016-01-29 15:07:25 +00:00
cpu.h target-tricore: Add FPU infrastructure 2016-03-23 09:22:48 +01:00
csfr.def target-tricore: Fix new typos 2015-01-15 10:44:13 +03:00
fpu_helper.c target-tricore: Add FPU infrastructure 2016-03-23 09:22:48 +01:00
helper.c target-tricore: Add FPU infrastructure 2016-03-23 09:22:48 +01:00
helper.h target-tricore: Add trap handling & SOVF/OVF traps 2016-02-25 12:54:42 +01:00
Makefile.objs target-tricore: Add FPU infrastructure 2016-03-23 09:22:48 +01:00
op_helper.c target-tricore: Fix helper_msub64_q_ssov not reseting OVF bit 2016-03-23 09:22:48 +01:00
translate.c target-tricore: Move general CHECK_REG_PAIR of decode_rrr_divide 2016-03-23 09:22:48 +01:00
tricore-defs.h target-tricore: Add target stubs and qom-cpu 2014-09-01 14:49:20 +01:00
tricore-opcodes.h target-tricore: Add FPU infrastructure 2016-03-23 09:22:48 +01:00