qemu/tcg/riscv
Richard Henderson fecccfcc54 tcg: Split INDEX_op_qemu_{ld,st}* for guest address size
For 32-bit hosts, we cannot simply rely on TCGContext.addr_bits,
as we need one or two host registers to represent the guest address.

Create the new opcodes and update all users.  Since we have not
yet eliminated TARGET_LONG_BITS, only one of the two opcodes will
ever be used, so we can get away with treating them the same in
the backends.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-16 20:07:20 -07:00
..
tcg-target-con-set.h tcg/riscv: Simplify constraints on qemu_ld/st 2023-05-11 09:53:41 +01:00
tcg-target-con-str.h tcg/riscv: Simplify constraints on qemu_ld/st 2023-05-11 09:53:41 +01:00
tcg-target.c.inc tcg: Split INDEX_op_qemu_{ld,st}* for guest address size 2023-05-16 20:07:20 -07:00
tcg-target.h tcg: Add INDEX_op_qemu_{ld,st}_i128 2023-05-16 16:30:25 -07:00