Peter Maydell 957e615503 target/arm: Implement ARMv8.3-CCIDX ... The ARMv8.3-CCIDX extension makes the CCSIDR_EL1 system ID registers have a format that uses the full 64 bit width of the register, and adds a new CCSIDR2 register so AArch32 can get at the high 32 bits. QEMU doesn't implement caches, so we just treat these ID registers as opaque values that are set to the correct constant values for each CPU. The only thing we need to do is allow 64-bit values in our cssidr[] array and provide the CCSIDR2 accessors. We don't set the CCIDX field in our 'max' CPU because the CCSIDR constant values we use are the same as the ones used by the Cortex-A57 and they are in the old 32-bit format. This means that the extra regdef added here is unused currently, but it means that whenever in the future we add a CPU that does need the new 64-bit format it will just work when we set the cssidr values and the ID registers for it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200224182626.29252-1-peter.maydell@linaro.org		2020-02-28 16:14:57 +00:00
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alpha
arm	target/arm: Implement ARMv8.3-CCIDX	2020-02-28 16:14:57 +00:00
cris
hppa
i386	Merge branch 'exec_rw_const_v4' of https://github.com/philmd/qemu into HEAD	2020-02-25 13:41:48 +01:00
lm32
m68k
microblaze
mips	target/mips: Separate FPU-related helpers into their own file	2020-02-04 08:53:54 +01:00
moxie
nios2
openrisc
ppc	target/ppc/cpu.h: Clean up comments in the struct CPUPPCState definition	2020-02-21 09:15:04 +11:00
riscv	target/riscv: progressively load the instruction during decode	2020-02-25 20:20:23 +00:00
s390x	s390x: Rename and use constants for short PSW address and mask	2020-02-27 11:10:29 +01:00
sh4
sparc
tilegx
tricore
unicore32
xtensa