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43888c2f18
stimecmp allows the supervisor mode to update stimecmp CSR directly to program the next timer interrupt. This CSR is part of the Sstc extension which was ratified recently. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220824221357.41070-3-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
38 lines
943 B
Meson
38 lines
943 B
Meson
# FIXME extra_args should accept files()
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gen = [
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decodetree.process('insn16.decode', extra_args: ['--static-decode=decode_insn16', '--insnwidth=16']),
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decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
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decodetree.process('XVentanaCondOps.decode', extra_args: '--static-decode=decode_XVentanaCodeOps'),
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]
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riscv_ss = ss.source_set()
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riscv_ss.add(gen)
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riscv_ss.add(files(
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'cpu.c',
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'cpu_helper.c',
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'csr.c',
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'fpu_helper.c',
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'gdbstub.c',
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'op_helper.c',
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'vector_helper.c',
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'bitmanip_helper.c',
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'translate.c',
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'm128_helper.c',
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'crypto_helper.c'
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))
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riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c'))
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riscv_softmmu_ss = ss.source_set()
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riscv_softmmu_ss.add(files(
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'arch_dump.c',
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'pmp.c',
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'debug.c',
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'monitor.c',
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'machine.c',
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'pmu.c',
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'time_helper.c'
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))
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target_arch += {'riscv': riscv_ss}
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target_softmmu_arch += {'riscv': riscv_softmmu_ss}
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