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https://gitlab.com/qemu-project/qemu
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4ea5fe997d
These inline helpers are all used by target specific code so move them out of the general header so we don't needlessly pollute the rest of the API with target specific stuff. Note we have to include cpu.h in semihosting as it was relying on a side effect before. Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20230302190846.2593720-21-alex.bennee@linaro.org> Message-Id: <20230303025805.625589-21-richard.henderson@linaro.org>
139 lines
3.5 KiB
C
139 lines
3.5 KiB
C
/*
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* TriCore gdb server stub
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*
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* Copyright (c) 2019 Bastian Koppelmann, Paderborn University
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "gdbstub/helpers.h"
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#define LCX_REGNUM 32
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#define FCX_REGNUM 33
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#define PCXI_REGNUM 34
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#define TRICORE_PSW_REGNUM 35
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#define TRICORE_PC_REGNUM 36
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#define ICR_REGNUM 37
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#define ISP_REGNUM 38
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#define BTV_REGNUM 39
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#define BIV_REGNUM 40
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#define SYSCON_REGNUM 41
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#define PMUCON0_REGNUM 42
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#define DMUCON_REGNUM 43
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static uint32_t tricore_cpu_gdb_read_csfr(CPUTriCoreState *env, int n)
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{
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switch (n) {
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case LCX_REGNUM:
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return env->LCX;
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case FCX_REGNUM:
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return env->FCX;
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case PCXI_REGNUM:
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return env->PCXI;
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case TRICORE_PSW_REGNUM:
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return psw_read(env);
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case TRICORE_PC_REGNUM:
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return env->PC;
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case ICR_REGNUM:
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return env->ICR;
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case ISP_REGNUM:
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return env->ISP;
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case BTV_REGNUM:
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return env->BTV;
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case BIV_REGNUM:
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return env->BIV;
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case SYSCON_REGNUM:
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return env->SYSCON;
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case PMUCON0_REGNUM:
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return 0; /* PMUCON0 */
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case DMUCON_REGNUM:
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return 0; /* DMUCON0 */
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default:
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return 0;
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}
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}
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static void tricore_cpu_gdb_write_csfr(CPUTriCoreState *env, int n,
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uint32_t val)
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{
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switch (n) {
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case LCX_REGNUM:
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env->LCX = val;
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break;
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case FCX_REGNUM:
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env->FCX = val;
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break;
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case PCXI_REGNUM:
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env->PCXI = val;
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break;
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case TRICORE_PSW_REGNUM:
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psw_write(env, val);
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break;
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case TRICORE_PC_REGNUM:
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env->PC = val;
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break;
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case ICR_REGNUM:
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env->ICR = val;
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break;
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case ISP_REGNUM:
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env->ISP = val;
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break;
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case BTV_REGNUM:
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env->BTV = val;
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break;
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case BIV_REGNUM:
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env->BIV = val;
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break;
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case SYSCON_REGNUM:
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env->SYSCON = val;
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break;
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}
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}
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int tricore_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
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{
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TriCoreCPU *cpu = TRICORE_CPU(cs);
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CPUTriCoreState *env = &cpu->env;
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if (n < 16) { /* data registers */
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return gdb_get_reg32(mem_buf, env->gpr_d[n]);
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} else if (n < 32) { /* address registers */
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return gdb_get_reg32(mem_buf, env->gpr_a[n - 16]);
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} else { /* csfr */
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return gdb_get_reg32(mem_buf, tricore_cpu_gdb_read_csfr(env, n));
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}
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return 0;
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}
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int tricore_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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{
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TriCoreCPU *cpu = TRICORE_CPU(cs);
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CPUTriCoreState *env = &cpu->env;
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uint32_t tmp;
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tmp = ldl_p(mem_buf);
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if (n < 16) { /* data registers */
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env->gpr_d[n] = tmp;
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} else if (n < 32) { /* address registers */
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env->gpr_a[n - 16] = tmp;
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} else {
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tricore_cpu_gdb_write_csfr(env, n, tmp);
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}
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return 4;
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}
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