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![Olaf Hering](/assets/img/avatar_default.png)
According to the 82371FB documentation (82371FB.pdf, 2.3.9. BMIBA-BUS
MASTER INTERFACE BASE ADDRESS REGISTER, April 1997), the register is
32bit wide. To properly reset it to default values, all 32bit need to be
cleared. Bit #0 "Resource Type Indicator (RTE)" needs to be enabled.
The initial change wrote just the lower 8 bit, leaving parts of the "Bus
Master Interface Base Address" address at bit 15:4 unchanged.
Fixes: e6a71ae327
("Add support for 82371FB (Step A1) and Improved support for 82371SB (Function 1)")
Signed-off-by: Olaf Hering <olaf@aepfle.de>
Reviewed-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230712074721.14728-1-olaf@aepfle.de>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
232 lines
6.5 KiB
C
232 lines
6.5 KiB
C
/*
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* QEMU IDE Emulation: PCI PIIX3/4 support.
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*
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* Copyright (c) 2003 Fabrice Bellard
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* Copyright (c) 2006 Openedhand Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* References:
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* [1] 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR,
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* 290550-002, Intel Corporation, April 1997.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "hw/pci/pci.h"
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#include "hw/ide/piix.h"
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#include "hw/ide/pci.h"
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#include "trace.h"
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static uint64_t bmdma_read(void *opaque, hwaddr addr, unsigned size)
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{
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BMDMAState *bm = opaque;
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uint32_t val;
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if (size != 1) {
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return ((uint64_t)1 << (size * 8)) - 1;
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}
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switch(addr & 3) {
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case 0:
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val = bm->cmd;
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break;
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case 2:
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val = bm->status;
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break;
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default:
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val = 0xff;
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break;
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}
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trace_bmdma_read(addr, val);
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return val;
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}
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static void bmdma_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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BMDMAState *bm = opaque;
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if (size != 1) {
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return;
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}
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trace_bmdma_write(addr, val);
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switch(addr & 3) {
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case 0:
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bmdma_cmd_writeb(bm, val);
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break;
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case 2:
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bmdma_status_writeb(bm, val);
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break;
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}
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}
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static const MemoryRegionOps piix_bmdma_ops = {
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.read = bmdma_read,
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.write = bmdma_write,
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};
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static void bmdma_setup_bar(PCIIDEState *d)
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{
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int i;
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memory_region_init(&d->bmdma_bar, OBJECT(d), "piix-bmdma-container", 16);
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for(i = 0;i < 2; i++) {
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BMDMAState *bm = &d->bmdma[i];
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memory_region_init_io(&bm->extra_io, OBJECT(d), &piix_bmdma_ops, bm,
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"piix-bmdma", 4);
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memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
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memory_region_init_io(&bm->addr_ioport, OBJECT(d),
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&bmdma_addr_ioport_ops, bm, "bmdma", 4);
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memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
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}
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}
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static void piix_ide_reset(DeviceState *dev)
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{
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PCIIDEState *d = PCI_IDE(dev);
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PCIDevice *pd = PCI_DEVICE(d);
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uint8_t *pci_conf = pd->config;
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int i;
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for (i = 0; i < 2; i++) {
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ide_bus_reset(&d->bus[i]);
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}
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/* PCI command register default value (0000h) per [1, p.48]. */
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pci_set_word(pci_conf + PCI_COMMAND, 0x0000);
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pci_set_word(pci_conf + PCI_STATUS,
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PCI_STATUS_DEVSEL_MEDIUM | PCI_STATUS_FAST_BACK);
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pci_set_long(pci_conf + 0x20, 0x1); /* BMIBA: 20-23h */
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}
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static bool pci_piix_init_bus(PCIIDEState *d, unsigned i, Error **errp)
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{
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static const struct {
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int iobase;
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int iobase2;
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int isairq;
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} port_info[] = {
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{0x1f0, 0x3f6, 14},
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{0x170, 0x376, 15},
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};
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int ret;
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ide_bus_init(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2);
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ret = ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase,
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port_info[i].iobase2);
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if (ret) {
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error_setg_errno(errp, -ret, "Failed to realize %s port %u",
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object_get_typename(OBJECT(d)), i);
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return false;
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}
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ide_bus_init_output_irq(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq));
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bmdma_init(&d->bus[i], &d->bmdma[i], d);
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ide_bus_register_restart_cb(&d->bus[i]);
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return true;
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}
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static void pci_piix_ide_realize(PCIDevice *dev, Error **errp)
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{
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PCIIDEState *d = PCI_IDE(dev);
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uint8_t *pci_conf = dev->config;
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pci_conf[PCI_CLASS_PROG] = 0x80; // legacy ATA mode
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bmdma_setup_bar(d);
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pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
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for (unsigned i = 0; i < 2; i++) {
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if (!pci_piix_init_bus(d, i, errp)) {
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return;
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}
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}
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}
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static void pci_piix_ide_exitfn(PCIDevice *dev)
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{
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PCIIDEState *d = PCI_IDE(dev);
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unsigned i;
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for (i = 0; i < 2; ++i) {
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memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
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memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
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}
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}
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/* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
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static void piix3_ide_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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dc->reset = piix_ide_reset;
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dc->vmsd = &vmstate_ide_pci;
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k->realize = pci_piix_ide_realize;
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k->exit = pci_piix_ide_exitfn;
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k->vendor_id = PCI_VENDOR_ID_INTEL;
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k->device_id = PCI_DEVICE_ID_INTEL_82371SB_1;
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k->class_id = PCI_CLASS_STORAGE_IDE;
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set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
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dc->hotpluggable = false;
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}
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static const TypeInfo piix3_ide_info = {
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.name = TYPE_PIIX3_IDE,
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.parent = TYPE_PCI_IDE,
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.class_init = piix3_ide_class_init,
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};
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/* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */
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static void piix4_ide_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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dc->reset = piix_ide_reset;
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dc->vmsd = &vmstate_ide_pci;
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k->realize = pci_piix_ide_realize;
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k->exit = pci_piix_ide_exitfn;
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k->vendor_id = PCI_VENDOR_ID_INTEL;
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k->device_id = PCI_DEVICE_ID_INTEL_82371AB;
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k->class_id = PCI_CLASS_STORAGE_IDE;
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set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
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dc->hotpluggable = false;
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}
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static const TypeInfo piix4_ide_info = {
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.name = TYPE_PIIX4_IDE,
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.parent = TYPE_PCI_IDE,
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.class_init = piix4_ide_class_init,
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};
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static void piix_ide_register_types(void)
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{
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type_register_static(&piix3_ide_info);
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type_register_static(&piix4_ide_info);
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}
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type_init(piix_ide_register_types)
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