mirror of
https://gitlab.com/qemu-project/qemu
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235948bf53
The current implementation initializes the stack pointer of AVR devices to 0. Although older AVR devices used to be like that, newer ones set it to RAMEND. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1525 Signed-off-by: Gihun Nam <gihun.nam@outlook.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <PH0P222MB0010877445B594724D40C924DEBDA@PH0P222MB0010.NAMP222.PROD.OUTLOOK.COM> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
462 lines
16 KiB
C
462 lines
16 KiB
C
/*
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* QEMU ATmega MCU
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*
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* Copyright (c) 2019-2020 Philippe Mathieu-Daudé
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*
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* This work is licensed under the terms of the GNU GPLv2 or later.
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* See the COPYING file in the top-level directory.
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "qemu/module.h"
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#include "qemu/units.h"
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#include "qapi/error.h"
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#include "exec/memory.h"
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#include "exec/address-spaces.h"
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#include "sysemu/sysemu.h"
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#include "hw/qdev-properties.h"
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#include "hw/sysbus.h"
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#include "qom/object.h"
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#include "hw/misc/unimp.h"
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#include "atmega.h"
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enum AtmegaPeripheral {
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POWER0, POWER1,
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GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF,
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GPIOG, GPIOH, GPIOI, GPIOJ, GPIOK, GPIOL,
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USART0, USART1, USART2, USART3,
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TIMER0, TIMER1, TIMER2, TIMER3, TIMER4, TIMER5,
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PERIFMAX
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};
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#define GPIO(n) (n + GPIOA)
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#define USART(n) (n + USART0)
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#define TIMER(n) (n + TIMER0)
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#define POWER(n) (n + POWER0)
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typedef struct {
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uint16_t addr;
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enum AtmegaPeripheral power_index;
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uint8_t power_bit;
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/* timer specific */
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uint16_t intmask_addr;
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uint16_t intflag_addr;
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bool is_timer16;
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} peripheral_cfg;
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struct AtmegaMcuClass {
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/*< private >*/
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SysBusDeviceClass parent_class;
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/*< public >*/
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const char *uc_name;
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const char *cpu_type;
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size_t flash_size;
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size_t eeprom_size;
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size_t sram_size;
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size_t io_size;
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size_t gpio_count;
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size_t adc_count;
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const uint8_t *irq;
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const peripheral_cfg *dev;
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};
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typedef struct AtmegaMcuClass AtmegaMcuClass;
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DECLARE_CLASS_CHECKERS(AtmegaMcuClass, ATMEGA_MCU,
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TYPE_ATMEGA_MCU)
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static const peripheral_cfg dev168_328[PERIFMAX] = {
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[USART0] = { 0xc0, POWER0, 1 },
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[TIMER2] = { 0xb0, POWER0, 6, 0x70, 0x37, false },
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[TIMER1] = { 0x80, POWER0, 3, 0x6f, 0x36, true },
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[POWER0] = { 0x64 },
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[TIMER0] = { 0x44, POWER0, 5, 0x6e, 0x35, false },
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[GPIOD] = { 0x29 },
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[GPIOC] = { 0x26 },
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[GPIOB] = { 0x23 },
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}, dev1280_2560[PERIFMAX] = {
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[USART3] = { 0x130, POWER1, 2 },
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[TIMER5] = { 0x120, POWER1, 5, 0x73, 0x3a, true },
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[GPIOL] = { 0x109 },
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[GPIOK] = { 0x106 },
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[GPIOJ] = { 0x103 },
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[GPIOH] = { 0x100 },
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[USART2] = { 0xd0, POWER1, 1 },
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[USART1] = { 0xc8, POWER1, 0 },
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[USART0] = { 0xc0, POWER0, 1 },
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[TIMER2] = { 0xb0, POWER0, 6, 0x70, 0x37, false }, /* TODO async */
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[TIMER4] = { 0xa0, POWER1, 4, 0x72, 0x39, true },
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[TIMER3] = { 0x90, POWER1, 3, 0x71, 0x38, true },
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[TIMER1] = { 0x80, POWER0, 3, 0x6f, 0x36, true },
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[POWER1] = { 0x65 },
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[POWER0] = { 0x64 },
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[TIMER0] = { 0x44, POWER0, 5, 0x6e, 0x35, false },
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[GPIOG] = { 0x32 },
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[GPIOF] = { 0x2f },
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[GPIOE] = { 0x2c },
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[GPIOD] = { 0x29 },
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[GPIOC] = { 0x26 },
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[GPIOB] = { 0x23 },
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[GPIOA] = { 0x20 },
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};
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enum AtmegaIrq {
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USART0_RXC_IRQ, USART0_DRE_IRQ, USART0_TXC_IRQ,
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USART1_RXC_IRQ, USART1_DRE_IRQ, USART1_TXC_IRQ,
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USART2_RXC_IRQ, USART2_DRE_IRQ, USART2_TXC_IRQ,
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USART3_RXC_IRQ, USART3_DRE_IRQ, USART3_TXC_IRQ,
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TIMER0_CAPT_IRQ, TIMER0_COMPA_IRQ, TIMER0_COMPB_IRQ,
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TIMER0_COMPC_IRQ, TIMER0_OVF_IRQ,
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TIMER1_CAPT_IRQ, TIMER1_COMPA_IRQ, TIMER1_COMPB_IRQ,
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TIMER1_COMPC_IRQ, TIMER1_OVF_IRQ,
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TIMER2_CAPT_IRQ, TIMER2_COMPA_IRQ, TIMER2_COMPB_IRQ,
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TIMER2_COMPC_IRQ, TIMER2_OVF_IRQ,
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TIMER3_CAPT_IRQ, TIMER3_COMPA_IRQ, TIMER3_COMPB_IRQ,
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TIMER3_COMPC_IRQ, TIMER3_OVF_IRQ,
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TIMER4_CAPT_IRQ, TIMER4_COMPA_IRQ, TIMER4_COMPB_IRQ,
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TIMER4_COMPC_IRQ, TIMER4_OVF_IRQ,
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TIMER5_CAPT_IRQ, TIMER5_COMPA_IRQ, TIMER5_COMPB_IRQ,
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TIMER5_COMPC_IRQ, TIMER5_OVF_IRQ,
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IRQ_COUNT
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};
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#define USART_IRQ_COUNT 3
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#define USART_RXC_IRQ(n) (n * USART_IRQ_COUNT + USART0_RXC_IRQ)
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#define USART_DRE_IRQ(n) (n * USART_IRQ_COUNT + USART0_DRE_IRQ)
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#define USART_TXC_IRQ(n) (n * USART_IRQ_COUNT + USART0_TXC_IRQ)
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#define TIMER_IRQ_COUNT 5
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#define TIMER_CAPT_IRQ(n) (n * TIMER_IRQ_COUNT + TIMER0_CAPT_IRQ)
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#define TIMER_COMPA_IRQ(n) (n * TIMER_IRQ_COUNT + TIMER0_COMPA_IRQ)
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#define TIMER_COMPB_IRQ(n) (n * TIMER_IRQ_COUNT + TIMER0_COMPB_IRQ)
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#define TIMER_COMPC_IRQ(n) (n * TIMER_IRQ_COUNT + TIMER0_COMPC_IRQ)
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#define TIMER_OVF_IRQ(n) (n * TIMER_IRQ_COUNT + TIMER0_OVF_IRQ)
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static const uint8_t irq168_328[IRQ_COUNT] = {
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[TIMER2_COMPA_IRQ] = 8,
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[TIMER2_COMPB_IRQ] = 9,
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[TIMER2_OVF_IRQ] = 10,
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[TIMER1_CAPT_IRQ] = 11,
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[TIMER1_COMPA_IRQ] = 12,
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[TIMER1_COMPB_IRQ] = 13,
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[TIMER1_OVF_IRQ] = 14,
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[TIMER0_COMPA_IRQ] = 15,
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[TIMER0_COMPB_IRQ] = 16,
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[TIMER0_OVF_IRQ] = 17,
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[USART0_RXC_IRQ] = 19,
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[USART0_DRE_IRQ] = 20,
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[USART0_TXC_IRQ] = 21,
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}, irq1280_2560[IRQ_COUNT] = {
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[TIMER2_COMPA_IRQ] = 14,
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[TIMER2_COMPB_IRQ] = 15,
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[TIMER2_OVF_IRQ] = 16,
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[TIMER1_CAPT_IRQ] = 17,
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[TIMER1_COMPA_IRQ] = 18,
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[TIMER1_COMPB_IRQ] = 19,
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[TIMER1_COMPC_IRQ] = 20,
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[TIMER1_OVF_IRQ] = 21,
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[TIMER0_COMPA_IRQ] = 22,
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[TIMER0_COMPB_IRQ] = 23,
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[TIMER0_OVF_IRQ] = 24,
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[USART0_RXC_IRQ] = 26,
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[USART0_DRE_IRQ] = 27,
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[USART0_TXC_IRQ] = 28,
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[TIMER3_CAPT_IRQ] = 32,
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[TIMER3_COMPA_IRQ] = 33,
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[TIMER3_COMPB_IRQ] = 34,
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[TIMER3_COMPC_IRQ] = 35,
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[TIMER3_OVF_IRQ] = 36,
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[USART1_RXC_IRQ] = 37,
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[USART1_DRE_IRQ] = 38,
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[USART1_TXC_IRQ] = 39,
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[TIMER4_CAPT_IRQ] = 42,
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[TIMER4_COMPA_IRQ] = 43,
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[TIMER4_COMPB_IRQ] = 44,
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[TIMER4_COMPC_IRQ] = 45,
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[TIMER4_OVF_IRQ] = 46,
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[TIMER5_CAPT_IRQ] = 47,
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[TIMER5_COMPA_IRQ] = 48,
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[TIMER5_COMPB_IRQ] = 49,
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[TIMER5_COMPC_IRQ] = 50,
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[TIMER5_OVF_IRQ] = 51,
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[USART2_RXC_IRQ] = 52,
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[USART2_DRE_IRQ] = 53,
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[USART2_TXC_IRQ] = 54,
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[USART3_RXC_IRQ] = 55,
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[USART3_DRE_IRQ] = 56,
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[USART3_TXC_IRQ] = 57,
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};
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static void connect_peripheral_irq(const AtmegaMcuClass *k,
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SysBusDevice *dev, int dev_irqn,
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DeviceState *cpu,
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unsigned peripheral_index)
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{
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int cpu_irq = k->irq[peripheral_index];
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if (!cpu_irq) {
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return;
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}
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/* FIXME move that to avr_cpu_set_int() once 'sample' board is removed */
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assert(cpu_irq >= 2);
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cpu_irq -= 2;
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sysbus_connect_irq(dev, dev_irqn, qdev_get_gpio_in(cpu, cpu_irq));
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}
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static void connect_power_reduction_gpio(AtmegaMcuState *s,
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const AtmegaMcuClass *k,
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DeviceState *cpu,
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unsigned peripheral_index)
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{
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unsigned power_index = k->dev[peripheral_index].power_index;
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assert(k->dev[power_index].addr);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->pwr[power_index - POWER0]),
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k->dev[peripheral_index].power_bit,
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qdev_get_gpio_in(cpu, 0));
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}
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static void atmega_realize(DeviceState *dev, Error **errp)
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{
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AtmegaMcuState *s = ATMEGA_MCU(dev);
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const AtmegaMcuClass *mc = ATMEGA_MCU_GET_CLASS(dev);
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DeviceState *cpudev;
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SysBusDevice *sbd;
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char *devname;
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size_t i;
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assert(mc->io_size <= 0x200);
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if (!s->xtal_freq_hz) {
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error_setg(errp, "\"xtal-frequency-hz\" property must be provided.");
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return;
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}
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/* CPU */
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object_initialize_child(OBJECT(dev), "cpu", &s->cpu, mc->cpu_type);
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object_property_set_uint(OBJECT(&s->cpu), "init-sp",
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mc->io_size + mc->sram_size - 1, &error_abort);
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qdev_realize(DEVICE(&s->cpu), NULL, &error_abort);
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cpudev = DEVICE(&s->cpu);
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/* SRAM */
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memory_region_init_ram(&s->sram, OBJECT(dev), "sram", mc->sram_size,
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&error_abort);
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memory_region_add_subregion(get_system_memory(),
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OFFSET_DATA + mc->io_size, &s->sram);
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/* Flash */
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memory_region_init_rom(&s->flash, OBJECT(dev),
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"flash", mc->flash_size, &error_fatal);
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memory_region_add_subregion(get_system_memory(), OFFSET_CODE, &s->flash);
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/*
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* I/O
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*
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* 0x00 - 0x1f: Registers
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* 0x20 - 0x5f: I/O memory
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* 0x60 - 0xff: Extended I/O
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*/
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s->io = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
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qdev_prop_set_string(s->io, "name", "I/O");
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qdev_prop_set_uint64(s->io, "size", mc->io_size);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(s->io), &error_fatal);
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sysbus_mmio_map_overlap(SYS_BUS_DEVICE(s->io), 0, OFFSET_DATA, -1234);
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/* Power Reduction */
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for (i = 0; i < POWER_MAX; i++) {
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int idx = POWER(i);
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if (!mc->dev[idx].addr) {
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continue;
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}
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devname = g_strdup_printf("power%zu", i);
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object_initialize_child(OBJECT(dev), devname, &s->pwr[i],
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TYPE_AVR_MASK);
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sysbus_realize(SYS_BUS_DEVICE(&s->pwr[i]), &error_abort);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->pwr[i]), 0,
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OFFSET_DATA + mc->dev[idx].addr);
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g_free(devname);
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}
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/* GPIO */
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for (i = 0; i < GPIO_MAX; i++) {
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int idx = GPIO(i);
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if (!mc->dev[idx].addr) {
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continue;
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}
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devname = g_strdup_printf("atmega-gpio-%c", 'a' + (char)i);
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create_unimplemented_device(devname,
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OFFSET_DATA + mc->dev[idx].addr, 3);
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g_free(devname);
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}
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/* USART */
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for (i = 0; i < USART_MAX; i++) {
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int idx = USART(i);
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if (!mc->dev[idx].addr) {
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continue;
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}
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devname = g_strdup_printf("usart%zu", i);
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object_initialize_child(OBJECT(dev), devname, &s->usart[i],
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TYPE_AVR_USART);
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qdev_prop_set_chr(DEVICE(&s->usart[i]), "chardev", serial_hd(i));
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sbd = SYS_BUS_DEVICE(&s->usart[i]);
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sysbus_realize(sbd, &error_abort);
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sysbus_mmio_map(sbd, 0, OFFSET_DATA + mc->dev[USART(i)].addr);
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connect_peripheral_irq(mc, sbd, 0, cpudev, USART_RXC_IRQ(i));
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connect_peripheral_irq(mc, sbd, 1, cpudev, USART_DRE_IRQ(i));
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connect_peripheral_irq(mc, sbd, 2, cpudev, USART_TXC_IRQ(i));
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connect_power_reduction_gpio(s, mc, DEVICE(&s->usart[i]), idx);
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g_free(devname);
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}
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/* Timer */
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for (i = 0; i < TIMER_MAX; i++) {
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int idx = TIMER(i);
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if (!mc->dev[idx].addr) {
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continue;
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}
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if (!mc->dev[idx].is_timer16) {
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create_unimplemented_device("avr-timer8",
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OFFSET_DATA + mc->dev[idx].addr, 5);
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create_unimplemented_device("avr-timer8-intmask",
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OFFSET_DATA
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+ mc->dev[idx].intmask_addr, 1);
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create_unimplemented_device("avr-timer8-intflag",
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OFFSET_DATA
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+ mc->dev[idx].intflag_addr, 1);
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continue;
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}
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devname = g_strdup_printf("timer%zu", i);
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object_initialize_child(OBJECT(dev), devname, &s->timer[i],
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TYPE_AVR_TIMER16);
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object_property_set_uint(OBJECT(&s->timer[i]), "cpu-frequency-hz",
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s->xtal_freq_hz, &error_abort);
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sbd = SYS_BUS_DEVICE(&s->timer[i]);
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sysbus_realize(sbd, &error_abort);
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sysbus_mmio_map(sbd, 0, OFFSET_DATA + mc->dev[idx].addr);
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sysbus_mmio_map(sbd, 1, OFFSET_DATA + mc->dev[idx].intmask_addr);
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sysbus_mmio_map(sbd, 2, OFFSET_DATA + mc->dev[idx].intflag_addr);
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connect_peripheral_irq(mc, sbd, 0, cpudev, TIMER_CAPT_IRQ(i));
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connect_peripheral_irq(mc, sbd, 1, cpudev, TIMER_COMPA_IRQ(i));
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connect_peripheral_irq(mc, sbd, 2, cpudev, TIMER_COMPB_IRQ(i));
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connect_peripheral_irq(mc, sbd, 3, cpudev, TIMER_COMPC_IRQ(i));
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connect_peripheral_irq(mc, sbd, 4, cpudev, TIMER_OVF_IRQ(i));
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connect_power_reduction_gpio(s, mc, DEVICE(&s->timer[i]), idx);
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g_free(devname);
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}
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create_unimplemented_device("avr-twi", OFFSET_DATA + 0x0b8, 6);
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create_unimplemented_device("avr-adc", OFFSET_DATA + 0x078, 8);
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create_unimplemented_device("avr-ext-mem-ctrl", OFFSET_DATA + 0x074, 2);
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create_unimplemented_device("avr-watchdog", OFFSET_DATA + 0x060, 1);
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create_unimplemented_device("avr-spi", OFFSET_DATA + 0x04c, 3);
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create_unimplemented_device("avr-eeprom", OFFSET_DATA + 0x03f, 3);
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}
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static Property atmega_props[] = {
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DEFINE_PROP_UINT64("xtal-frequency-hz", AtmegaMcuState,
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xtal_freq_hz, 0),
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DEFINE_PROP_END_OF_LIST()
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};
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static void atmega_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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dc->realize = atmega_realize;
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device_class_set_props(dc, atmega_props);
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/* Reason: Mapped at fixed location on the system bus */
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dc->user_creatable = false;
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}
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static void atmega168_class_init(ObjectClass *oc, void *data)
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{
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AtmegaMcuClass *amc = ATMEGA_MCU_CLASS(oc);
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amc->cpu_type = AVR_CPU_TYPE_NAME("avr5");
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amc->flash_size = 16 * KiB;
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amc->eeprom_size = 512;
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amc->sram_size = 1 * KiB;
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amc->io_size = 256;
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amc->gpio_count = 23;
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amc->adc_count = 6;
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amc->irq = irq168_328;
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amc->dev = dev168_328;
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};
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static void atmega328_class_init(ObjectClass *oc, void *data)
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{
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AtmegaMcuClass *amc = ATMEGA_MCU_CLASS(oc);
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amc->cpu_type = AVR_CPU_TYPE_NAME("avr5");
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amc->flash_size = 32 * KiB;
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amc->eeprom_size = 1 * KiB;
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amc->sram_size = 2 * KiB;
|
|
amc->io_size = 256;
|
|
amc->gpio_count = 23;
|
|
amc->adc_count = 6;
|
|
amc->irq = irq168_328;
|
|
amc->dev = dev168_328;
|
|
};
|
|
|
|
static void atmega1280_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
AtmegaMcuClass *amc = ATMEGA_MCU_CLASS(oc);
|
|
|
|
amc->cpu_type = AVR_CPU_TYPE_NAME("avr51");
|
|
amc->flash_size = 128 * KiB;
|
|
amc->eeprom_size = 4 * KiB;
|
|
amc->sram_size = 8 * KiB;
|
|
amc->io_size = 512;
|
|
amc->gpio_count = 86;
|
|
amc->adc_count = 16;
|
|
amc->irq = irq1280_2560;
|
|
amc->dev = dev1280_2560;
|
|
};
|
|
|
|
static void atmega2560_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
AtmegaMcuClass *amc = ATMEGA_MCU_CLASS(oc);
|
|
|
|
amc->cpu_type = AVR_CPU_TYPE_NAME("avr6");
|
|
amc->flash_size = 256 * KiB;
|
|
amc->eeprom_size = 4 * KiB;
|
|
amc->sram_size = 8 * KiB;
|
|
amc->io_size = 512;
|
|
amc->gpio_count = 54;
|
|
amc->adc_count = 16;
|
|
amc->irq = irq1280_2560;
|
|
amc->dev = dev1280_2560;
|
|
};
|
|
|
|
static const TypeInfo atmega_mcu_types[] = {
|
|
{
|
|
.name = TYPE_ATMEGA168_MCU,
|
|
.parent = TYPE_ATMEGA_MCU,
|
|
.class_init = atmega168_class_init,
|
|
}, {
|
|
.name = TYPE_ATMEGA328_MCU,
|
|
.parent = TYPE_ATMEGA_MCU,
|
|
.class_init = atmega328_class_init,
|
|
}, {
|
|
.name = TYPE_ATMEGA1280_MCU,
|
|
.parent = TYPE_ATMEGA_MCU,
|
|
.class_init = atmega1280_class_init,
|
|
}, {
|
|
.name = TYPE_ATMEGA2560_MCU,
|
|
.parent = TYPE_ATMEGA_MCU,
|
|
.class_init = atmega2560_class_init,
|
|
}, {
|
|
.name = TYPE_ATMEGA_MCU,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(AtmegaMcuState),
|
|
.class_size = sizeof(AtmegaMcuClass),
|
|
.class_init = atmega_class_init,
|
|
.abstract = true,
|
|
}
|
|
};
|
|
|
|
DEFINE_TYPES(atmega_mcu_types)
|