mirror of
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![Philippe Mathieu-Daudé](/assets/img/avatar_default.png)
The Nios II target is deprecated since v8.2 in commit 9997771bc1
("target/nios2: Deprecate the Nios II architecture").
Remove:
- Buildsys / CI infra
- User emulation
- System emulation (10m50-ghrd & nios2-generic-nommu machines)
- Tests
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Marek Vasut <marex@denx.de>
Message-Id: <20240327144806.11319-3-philmd@linaro.org>
185 lines
5.9 KiB
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185 lines
5.9 KiB
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Emulation
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=========
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QEMU's Tiny Code Generator (TCG) provides the ability to emulate a
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number of CPU architectures on any supported host platform. Both
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:ref:`System Emulation` and :ref:`User Mode Emulation` are supported
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depending on the guest architecture.
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.. list-table:: Supported Guest Architectures for Emulation
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:widths: 30 10 10 50
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:header-rows: 1
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* - Architecture (qemu name)
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- System
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- User
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- Notes
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* - Alpha
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- Yes
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- Yes
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- Legacy 64 bit RISC ISA developed by DEC
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* - Arm (arm, aarch64)
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- :ref:`Yes<ARM-System-emulator>`
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- Yes
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- Wide range of features, see :ref:`Arm Emulation` for details
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* - AVR
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- :ref:`Yes<AVR-System-emulator>`
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- No
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- 8 bit micro controller, often used in maker projects
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* - Cris
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- Yes
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- Yes
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- Embedded RISC chip developed by AXIS
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* - Hexagon
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- No
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- Yes
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- Family of DSPs by Qualcomm
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* - PA-RISC (hppa)
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- Yes
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- Yes
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- A legacy RISC system used in HP's old minicomputers
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* - x86 (i386, x86_64)
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- :ref:`Yes<QEMU-PC-System-emulator>`
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- Yes
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- The ubiquitous desktop PC CPU architecture, 32 and 64 bit.
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* - Loongarch
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- Yes
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- Yes
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- A MIPS-like 64bit RISC architecture developed in China
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* - m68k
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- :ref:`Yes<ColdFire-System-emulator>`
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- Yes
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- Motorola 68000 variants and ColdFire
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* - Microblaze
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- Yes
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- Yes
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- RISC based soft-core by Xilinx
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* - MIPS (mips*)
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- :ref:`Yes<MIPS-System-emulator>`
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- Yes
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- Venerable RISC architecture originally out of Stanford University
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* - OpenRISC
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- :ref:`Yes<OpenRISC-System-emulator>`
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- Yes
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- Open source RISC architecture developed by the OpenRISC community
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* - Power (ppc, ppc64)
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- :ref:`Yes<PowerPC-System-emulator>`
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- Yes
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- A general purpose RISC architecture now managed by IBM
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* - RISC-V
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- :ref:`Yes<RISC-V-System-emulator>`
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- Yes
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- An open standard RISC ISA maintained by RISC-V International
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* - RX
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- :ref:`Yes<RX-System-emulator>`
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- No
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- A 32 bit micro controller developed by Renesas
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* - s390x
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- :ref:`Yes<s390x-System-emulator>`
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- Yes
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- A 64 bit CPU found in IBM's System Z mainframes
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* - sh4
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- Yes
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- Yes
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- A 32 bit RISC embedded CPU developed by Hitachi
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* - SPARC (sparc, sparc64)
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- :ref:`Yes<Sparc32-System-emulator>`
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- Yes
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- A RISC ISA originally developed by Sun Microsystems
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* - Tricore
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- Yes
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- No
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- A 32 bit RISC/uController/DSP developed by Infineon
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* - Xtensa
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- :ref:`Yes<Xtensa-System-emulator>`
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- Yes
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- A configurable 32 bit soft core now owned by Cadence
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A number of features are only available when running under
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emulation including :ref:`Record/Replay<replay>` and :ref:`TCG Plugins`.
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.. _Semihosting:
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Semihosting
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-----------
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Semihosting is a feature defined by the owner of the architecture to
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allow programs to interact with a debugging host system. On real
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hardware this is usually provided by an In-circuit emulator (ICE)
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hooked directly to the board. QEMU's implementation allows for
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semihosting calls to be passed to the host system or via the
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``gdbstub``.
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Generally semihosting makes it easier to bring up low level code before a
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more fully functional operating system has been enabled. On QEMU it
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also allows for embedded micro-controller code which typically doesn't
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have a full libc to be run as "bare-metal" code under QEMU's user-mode
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emulation. It is also useful for writing test cases and indeed a
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number of compiler suites as well as QEMU itself use semihosting calls
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to exit test code while reporting the success state.
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Semihosting is only available using TCG emulation. This is because the
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instructions to trigger a semihosting call are typically reserved
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causing most hypervisors to trap and fault on them.
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.. warning::
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Semihosting inherently bypasses any isolation there may be between
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the guest and the host. As a result a program using semihosting can
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happily trash your host system. Some semihosting calls (e.g.
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``SYS_READC``) can block execution indefinitely. You should only
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ever run trusted code with semihosting enabled.
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Redirection
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~~~~~~~~~~~
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Semihosting calls can be re-directed to a (potentially remote) gdb
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during debugging via the :ref:`gdbstub<GDB usage>`. Output to the
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semihosting console is configured as a ``chardev`` so can be
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redirected to a file, pipe or socket like any other ``chardev``
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device.
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Supported Targets
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~~~~~~~~~~~~~~~~~
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Most targets offer similar semihosting implementations with some
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minor changes to define the appropriate instruction to encode the
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semihosting call and which registers hold the parameters. They tend to
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presents a simple POSIX-like API which allows your program to read and
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write files, access the console and some other basic interactions.
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For full details of the ABI for a particular target, and the set of
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calls it provides, you should consult the semihosting specification
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for that architecture.
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.. note::
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QEMU makes an implementation decision to implement all file
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access in ``O_BINARY`` mode. The user-visible effect of this is
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regardless of the text/binary mode the program sets QEMU will
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always select a binary mode ensuring no line-terminator conversion
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is performed on input or output. This is because gdb semihosting
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support doesn't make the distinction between the modes and
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magically processing line endings can be confusing.
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.. list-table:: Guest Architectures supporting Semihosting
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:widths: 10 10 80
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:header-rows: 1
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* - Architecture
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- Modes
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- Specification
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* - Arm
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- System and User-mode
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- https://github.com/ARM-software/abi-aa/blob/main/semihosting/semihosting.rst
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* - m68k
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- System
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- https://sourceware.org/git/?p=newlib-cygwin.git;a=blob;f=libgloss/m68k/m68k-semi.txt;hb=HEAD
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* - MIPS
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- System
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- Unified Hosting Interface (MD01069)
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* - RISC-V
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- System and User-mode
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- https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc
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* - Xtensa
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- System
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- Tensilica ISS SIMCALL
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