Paul Brook d4c430a80f Large page TLB flush ... QEMU uses a fixed page size for the CPU TLB. If the guest uses large pages then we effectively split these into multiple smaller pages, and populate the corresponding TLB entries on demand. When the guest invalidates the TLB by virtual address we must invalidate all entries covered by the large page. However the address used to invalidate the entry may not be present in the QEMU TLB, so we do not know which regions to clear. Implementing a full vaiable size TLB is hard and slow, so just keep a simple address/mask pair to record which addresses may have been mapped by large pages. If the guest invalidates this region then flush the whole TLB. Signed-off-by: Paul Brook <paul@codesourcery.com>		2010-03-17 02:44:41 +00:00
..
cpu.h	Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h.	2010-03-12 16:28:24 +00:00
crisv10-decode.h	Update to a hopefully more future proof FSF address	2010-03-07 15:48:43 +00:00
crisv32-decode.h	Update to a hopefully more future proof FSF address	2009-07-16 20:47:01 +00:00
exec.h	kill regs_to_env and env_to_regs	2010-01-19 16:31:02 -06:00
helper.c	Large page TLB flush	2010-03-17 02:44:41 +00:00
helper.h	CRIS: Purify some of the flag evaluation helpers.	2009-01-07 23:38:41 +00:00
machine.c	Convert machine registration to use module init functions	2009-05-21 08:47:55 -05:00
mmu.c	CRIS: Segmented addressing only for kernel mode.	2009-10-10 17:34:27 +02:00
mmu.h	CRIS: cris_mmu_result_t -> cris_mmu_result	2009-04-25 15:51:53 +02:00
op_helper.c	crisv10: Always clear the V and C flags on btst.	2010-02-15 11:20:30 +01:00
opcode-cris.h	Update to a hopefully more future proof FSF address	2009-07-16 20:47:01 +00:00
translate.c	cris: Add support for CRISv10 translation.	2010-02-15 12:18:57 +01:00
translate_v10.c	Update to a hopefully more future proof FSF address	2010-03-07 15:48:43 +00:00