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f6f72338d8
This patch adds XVentanaCondOps support to the RISC-V disassembler. Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230612111034.3955227-8-christoph.muellner@vrull.eu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
41 lines
1 KiB
C
41 lines
1 KiB
C
/*
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* QEMU RISC-V Disassembler for xventana.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "disas/riscv.h"
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#include "disas/riscv-xventana.h"
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typedef enum {
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/* 0 is reserved for rv_op_illegal. */
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ventana_op_vt_maskc = 1,
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ventana_op_vt_maskcn = 2,
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} rv_ventana_op;
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const rv_opcode_data ventana_opcode_data[] = {
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{ "vt.illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
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{ "vt.maskc", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "vt.maskcn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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};
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void decode_xventanacondops(rv_decode *dec, rv_isa isa)
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{
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rv_inst inst = dec->inst;
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rv_opcode op = rv_op_illegal;
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switch (((inst >> 0) & 0b11)) {
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case 3:
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switch (((inst >> 2) & 0b11111)) {
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case 30:
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switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) {
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case 6: op = ventana_op_vt_maskc; break;
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case 7: op = ventana_op_vt_maskcn; break;
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}
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break;
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}
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break;
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}
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dec->op = op;
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}
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