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![Richard Henderson](/assets/img/avatar_default.png)
Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Tested-by: Leon Alrae <leon.alrae@imgtec.com> Message-id: 1410626734-3804-19-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
172 lines
4.5 KiB
C
172 lines
4.5 KiB
C
/*
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* QEMU MIPS CPU
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*
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#include "cpu.h"
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#include "kvm_mips.h"
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#include "qemu-common.h"
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#include "sysemu/kvm.h"
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static void mips_cpu_set_pc(CPUState *cs, vaddr value)
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{
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MIPSCPU *cpu = MIPS_CPU(cs);
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CPUMIPSState *env = &cpu->env;
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env->active_tc.PC = value & ~(target_ulong)1;
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if (value & 1) {
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env->hflags |= MIPS_HFLAG_M16;
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} else {
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env->hflags &= ~(MIPS_HFLAG_M16);
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}
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}
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static void mips_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
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{
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MIPSCPU *cpu = MIPS_CPU(cs);
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CPUMIPSState *env = &cpu->env;
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env->active_tc.PC = tb->pc;
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env->hflags &= ~MIPS_HFLAG_BMASK;
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env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
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}
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static bool mips_cpu_has_work(CPUState *cs)
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{
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MIPSCPU *cpu = MIPS_CPU(cs);
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CPUMIPSState *env = &cpu->env;
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bool has_work = false;
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/* It is implementation dependent if non-enabled interrupts
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wake-up the CPU, however most of the implementations only
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check for interrupts that can be taken. */
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if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
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cpu_mips_hw_interrupts_pending(env)) {
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has_work = true;
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}
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/* MIPS-MT has the ability to halt the CPU. */
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if (env->CP0_Config3 & (1 << CP0C3_MT)) {
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/* The QEMU model will issue an _WAKE request whenever the CPUs
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should be woken up. */
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if (cs->interrupt_request & CPU_INTERRUPT_WAKE) {
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has_work = true;
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}
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if (!mips_vpe_active(env)) {
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has_work = false;
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}
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}
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return has_work;
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}
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/* CPUClass::reset() */
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static void mips_cpu_reset(CPUState *s)
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{
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MIPSCPU *cpu = MIPS_CPU(s);
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MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
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CPUMIPSState *env = &cpu->env;
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mcc->parent_reset(s);
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memset(env, 0, offsetof(CPUMIPSState, mvp));
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tlb_flush(s, 1);
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cpu_state_reset(env);
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#ifndef CONFIG_USER_ONLY
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if (kvm_enabled()) {
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kvm_mips_reset_vcpu(cpu);
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}
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#endif
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}
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static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev);
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cpu_reset(cs);
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qemu_init_vcpu(cs);
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mcc->parent_realize(dev, errp);
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}
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static void mips_cpu_initfn(Object *obj)
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{
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CPUState *cs = CPU(obj);
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MIPSCPU *cpu = MIPS_CPU(obj);
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CPUMIPSState *env = &cpu->env;
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cs->env_ptr = env;
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cpu_exec_init(env);
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if (tcg_enabled()) {
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mips_tcg_init();
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}
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}
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static void mips_cpu_class_init(ObjectClass *c, void *data)
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{
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MIPSCPUClass *mcc = MIPS_CPU_CLASS(c);
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CPUClass *cc = CPU_CLASS(c);
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DeviceClass *dc = DEVICE_CLASS(c);
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mcc->parent_realize = dc->realize;
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dc->realize = mips_cpu_realizefn;
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mcc->parent_reset = cc->reset;
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cc->reset = mips_cpu_reset;
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cc->has_work = mips_cpu_has_work;
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cc->do_interrupt = mips_cpu_do_interrupt;
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cc->cpu_exec_interrupt = mips_cpu_exec_interrupt;
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cc->dump_state = mips_cpu_dump_state;
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cc->set_pc = mips_cpu_set_pc;
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cc->synchronize_from_tb = mips_cpu_synchronize_from_tb;
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cc->gdb_read_register = mips_cpu_gdb_read_register;
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cc->gdb_write_register = mips_cpu_gdb_write_register;
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#ifdef CONFIG_USER_ONLY
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cc->handle_mmu_fault = mips_cpu_handle_mmu_fault;
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#else
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cc->do_unassigned_access = mips_cpu_unassigned_access;
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cc->do_unaligned_access = mips_cpu_do_unaligned_access;
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cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
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#endif
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cc->gdb_num_core_regs = 73;
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}
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static const TypeInfo mips_cpu_type_info = {
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.name = TYPE_MIPS_CPU,
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.parent = TYPE_CPU,
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.instance_size = sizeof(MIPSCPU),
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.instance_init = mips_cpu_initfn,
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.abstract = false,
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.class_size = sizeof(MIPSCPUClass),
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.class_init = mips_cpu_class_init,
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};
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static void mips_cpu_register_types(void)
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{
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type_register_static(&mips_cpu_type_info);
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}
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type_init(mips_cpu_register_types)
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